2. FPGA

4. ABSTRACT- 1. Design three (15,k) BCH Encoders using VHDL 2.Implementation of (15,k) BCH Encoder on Xilinx Spartan3 FPGA 3. Simulation & synthesis using Xilinx ISE 10.1 4. Design & Implemention of the Parallel system

5. OBJECTIVE 1.Design single bit error-correcring BCH code (15,11,1) 2.Design double bit error-correcting BCH code (15,7,2) 3.Design three bit error-correcting BCH code (15,5,3) 4.Design parallel system

6. Codes:- Linear Block Codes Hamming codes Cyclic codes BCH (Bose-Chaudhuri-Hocquenghem) codes

7. METHOLOGY Genearted Polynomial of Binary Generated BCH Code over GF(2 4 ) 1.Block length : n = 2 m -1 2. Number of information bits: k ≥ n – m*t 3. Minimum distance: dmin ≥ 2t +1 4. g (x) = LCM {φ1 (x),φ2 (x),........,φ2t (x)}) For (15, k) BCH code minimal polynomials Φ1 (x) = 1+x+x 4 φ3 (x) =1+x+x 2 +x 3 +x 4 φ5 (x) = 1+x+x 2

8. Single error correcting BCH code length n=2 4 -1=15 Generated Polynomial:- g 1 (x) = φ (x) = 1+x+x 4 Highest degree = 4 i.e (n-k = 4), code (15, 11) cyclic code with dmin ≥ 3 Double error correcting BCH Code length n = 15 Generated Polynomial :- g ( x) = LCM {φ1 (x),φ3 (x)} g ( x) = 1+x+x 4 +x 6 +x 7 +x 8 Highest degree =8 i.e (n-k = 8), code (15, 7) cyclic code with dmin ≥ 6 Triple error correcting BCH code length n = 15 Generated Polynomial :- g ( x) = LCM {φ1 (x),φ3 (x),φ5 (x)} g ( x) = 1+x+x 2 +x 4 +x 5 +x 7 +x 8 +x 10 Here highest degree = 10 i.e (n-k = 10), code (15, 5) cyclic code with dmin ≥ 7.

9. DESIGN OF CIRCUIT Implement BCH encoder with a serial linear feedback shift register (LFSR) architecture Encode BCH codeword c(x) = x n-k ∗ i(x)+ b(x) c(x) = c0 + c1 x +..... + cn−l x n−l i(x) = i0 + i1 x +..... + ik −l x k-1 b(x ) = b0 + b1 x +..... + cm−l x m-1 and cj, ij, bj ∈ GF(2). Polynomial x n-k * i(x) = q(x) * q(x) – b(x) g(x)=1+ g 1 (x)+........+g n-k-l (x n-k-l )+x n-k k data present in the codeword. Obtained remainder b(x) in a linear (n-k)-stage shift register with feedback connections corresponding to the coefficients of the generator polynomial g(x)=1+ g 1 (x)+........+g n-k-l (x n-k-l )+x n-k

10. LFSR

11. Design of Encoder for (15, 11, 1) BCH Code Design Encoder for (15, 11, 1) single error correcting BCH code by organizing LFSR with generated polynomial 1+x+x 4 Implement on Spartan 3 S1000 FPGA of Xilinx. RTL view & Schematic by synthesis with Xilinx ISE 10.1, shown in Fig 3 and Fig. 4 Figure 3. RTL for (15, 11, 1) BCH Encoder

12. Figure 4. Schematic for (15, 11, 1) BCH Encoder

13. Design of Encoder for (15, 7, 2) BCH Code Double error correcting BCH code designed by organizing LFSR with generated Polynomial 1+x 4 +x 6 +x 7 +x 8 implemented on Spartan 3S1000 FPGA of Xilinx. RTL view & Schematic is generated by synthesis with Xilinx ISE 10.1, shown in Fig. 5and Fig. 6. Figure 5. RTL for (15, 7, 2) BCH Conder

14. Figure 6. Schematic for (15, 7, 2) BCH Encoder

15. Design of Encoder for (15, 5, 3) BCH Code Encoder for (15, 5, 3) triple error correcting Design BCH code by organizing LFSR with generated Polynomial 1+x 2 +x 4 +x 5 +x 8 +x 10 Implement on Spartan 3S1000 FPGA of Xilinx. The RTL view and Schematic is generated by synthesis with Xilinx ISE 10.1, which are shown in Fig.7 and Fig. 8. Figure 7. RTL for (15, 5, 3) BCH Encoder

16. Figure 8. Schematic for (15, 5, 3) BCH Encoder

17. RESULT AND DISCUSSION Simulation Waveform Result of (15, 11, 1) BCH Encoder

18. Simulation Waveform Result of (15, 7, 2) BCH Encoder

19. . Simulation Waveform Result of (15, 5, 3) BCH Encoder

20. Comparison of Performance Between Single, Double and Tripple Error Correcting (15, k) BCH Code Device Utlization and Timing Summary Component Utlization/Time (15,11,1) BCH Encoder (15,7,2) BCH Encoder (15,5,3) BCH Encoder No. of Slices 689 No. of Slice FF91215 4 input LUTs121416 Number of IOs555 Simulation clock20ns Maxm. Combinational path delay 9.159ns Maxm. Output required 8.81ns8.73ns8.57ns Total CPU time to Xst completion 6.13ns5.9sec5.7 sec

21. V. CONCLUSION Next stage of (15,k) BCH encoder is not possible so we use parallel system for (15,11,1),(15,7,2) & (15,5,3) for correcting data at receiver side according to requirement. The speed and device utilization can be improved by adopting parallel approach methods.

22. REFERENCES [1] M.Y. Rhee - “Error Correcting Coding Theory”, McGraw-H Singapore, 1989. [2] S. Lin, and D.J. Costello Jr. - “Error Control Coding”, Prentice-Hall,New Jersey, 1983. [3] E. R. Berlekamp, “Algebraic coding theory”, McGraw-Hill, New York, 1968. [4] R.E. Blahut, “Theory and practice of error-control codes”, Addison- Wesley, Reading, MA, 1983 [5] S. B. Wicker, Error Control Systems for Digital Communication andStorage. Upper Saddle River, New Jersey 075458: Prentice Hall, Inc,1995. [6] Berlekamp, E.R., Peile, R.E. and Pope, S.P. (1987), "The applicationof error control to communications", IEEE Communication Magazine, 25, no.4, pp 40-57. [7] Shu Lin, Daniel J. Castello, “Error control coding, Fundamentals and applications”, Premtice-Hall, New Jersey, 1983, Pages 15-50. [8] Shu Lin, Daniel J. Castello, “Error control coding, Fundamentals and applications”, Premtice-Hall, New Jersey, 1983, Page 141-182. [9] W.W. Peterson, “Encoding and error-correction procedures or theBose-Chaudhuri Codes”, IRE Trans. Inf. Theory, IT-6, pp. 459- 470, September 1960.