1. TIMING DETECTOR ELECTRONICS FRONT END ELECTRONICS - NINO JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

2. READOUT CHAIN OVERVIEW To DAQ DIGITZER BOARD MPPC Detector connectors 32ch NINO BOARD connectors feedthroughfeedthrough 32ch NINO BOARD HPTDC/SAMPIC JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

3. FRONT-END ELECTRONICS The FE board is based on a NINO32 ASIC (CERN) Connects to the SiPM board Sends data to the HPTDC mezzanine m that sits on a Digitizer Motherboard DAQ BOARD MPPC Dete ctor connectors feedthroughfeedthrough 32ch NINO BOARD HPTDC/ SAMPIC JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

4. NINO ASIC CHARACTERISTICS Differential Threshold controlled via SPI DAC Set “minus” point at 1V Set “plus” from 1V to 2v5 Stretch is “on” ( off also works) Hysteresis is “on” (fixed) Differential impedance is set to 30ohms By PCB design and by external resistors External Test Pulse input Power 1V5 (output) 180mA 2V5 (DAC ref and NINO core) 280mA JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

5. PERFORMANCE SUMMARY jitter is for 10-20 pF JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

6. IRPICS 2 JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

7. IRPICS 2 Wire bond PCB design Globtop protection with PCB frame glued on pcb JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

8. STRETCHER JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

9. NINO BOARD POWER/SIGNAL CONNECTOR +1.5V and 2.5V from PSU SPI for DAC To SIPM To HPTDC TH+ preset to 1,25V DAC – diff threshold Adj– diff threshold JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015

10. NINO PRODUCTION AND PLANS We have now 6 NINO boards assembled Need to modify the resistors for test pulse Threshold adjust by potentiometers or DAC Tests in the lab to understand fully the NINO pulses and cabling effects Using Torch Readout system (C.Carpinteiro) Setup may later be used to qualify the HPTDC mezzanines (depends on Digitizer board availability) Understand effect of different SIPM input signal terminations JOSE DA SILVA –CT-PPS TIMING ENGINEERING REVIEW /10-11-2015