1. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

2. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Visual Status 2 Rx_mac2buf I2C Fifo 31 TDCs TDC 0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

3. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Done: ◦ LM32 + WB-Crossbar + DPRAM + UART ◦ Soft-PLL FMC layout ◦ WR without PCI-express Currently: ◦ Deterministic PHY ◦ Soft PLL (hardware + software). First goal: lock onto a 125 MHz xtal and phase shift under control of LM32 via UART To do (in order of priority): ◦ Endpoint (= MAC) <= Complex! ◦ Mini-nic <= Complex! ◦ Fabric redirector <= probably less complex ◦ PPS generator <= relatively straightforward ◦ 1-wire, SysCon <= easy? Status Listing 3

4. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Remove R16, R17, R21, R22, R23, R24 Add a jumper to connect TDO/TDI (FMC D30 is LTDO GBX pin G1) And (FMC D31 is LTD1 GBX pin D1) Replace U3 MCP1825S25 for MCP1825S18 Soft-PLL FMC 4

5. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Setup (Master -> Slave -> Master) 5 Soft-PLL FMC (DAC + VCXO)  Reference Clk = Currently KC705 crystal X3 Count Start Stop Master SFP Slave Rx Tx SFP RxUsrClk TxUsrClk RxUsrClk Tx Rx DACDPLL Fine time Coarse time

6. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Setup (Master -> Slave -> Master) 6 Master Soft-PLL FMC (DAC + VCXO) Stop Start Slave IsCharExt Soft-PLL FMC (DAC + VCXO) Cable Delay Master -> Slave Cable Delay Slave -> Master

7. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Setup (Slave clock distribution EASE test design) 7 GTXE2_CHANNEL IBUFDS_ GTE2 TXOUTCLK_OUT clk_gtx_i BUFG RXOUTCLK_OUT rx_rec_clkRXUSRCLK_IN RXUSRCLK2_IN TXUSRCLK_IN TXUSRCLK2_IN GTREFCLK0_IN wr_gtx_phy_kintex7.vhd Entity: wr_gtx_phy_kintex7 FPGA_Slave.vhd clk_125m_pllref_p_i clk_125m_pllref_n_i SoftPLL FMC DAC1 DAC2 VCXO 20MHz VCXO 25MHz CLK20_VCXO CDCM 61004 fpga_pll_ref_clk_123_p_i fpga_pll_ref_clk_123_n_i BUFG clk_ref_i dac_dpll dac_hpll Clk_20m_vcxo_i DPLL RxClk TxClk PLL25DAC1_SYNC_N PLL25DAC_DIN PLL25DAC_SCLK PLL25DAC2_SYNC_N ‘1’ gtx_dedicated_clk

8. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KC705 crystal X3 is of target frequency 8 Changed to 27 pf Frequency of the (“Master Node”) crystal ~ +25 ppm off the target (SGMIICLK_Q0 = 125.003140). The “Slave Node” VCXO doesn’t lock (out of VCXO pulling range). Soft-PLL FMC U12 outputs 124.999535 (midrange) which is ~ -4 ppm of target. Change C93, C94 => master frequency =125.000500 => VCXO Locks!

9. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Setup (Master -> Slave -> Master) 9 BitSlide (= Master BitSlide + Slave BitSlide) Master KC705 Soft-PLL FMC (DAC + VCXO) Start Stop Slave KC705 IsCharExt FMC XM105 Debug Card FMC XM105 Debug Card StartStopIsCharExt MS delaySM delay

10. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Setup (Master -> Slave -> Master) 10 Measured (on osciloscope) 859,3 ns in this test setup Determinism is proven since this equation holds:

11. May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology 11 GTXE2_CHANNEL gtx_dedicated_clk TXOUTCLK_OUT clk_gtx _i BUFG RXOUTCLK_OUT rx_rec_clkRXUSRCLK_IN RXUSRCLK2_IN TXUSRCLK_IN TXUSRCLK2_IN tx_out_clk GTREFCLK0_IN rx_rbclk_o wr_gtx_phy_kintex7.vhd Entity: wr_gtx_phy_kintex7 Kc705_top.vhd Entity: kc705_top IBUFGD S clk_125m_pllref PLL_BASE Cmp_dmtd_clk_ pll pllout_clk_dmtd (125.x MHz) Gc_extend_pulse ? Clk_i BUFG CPLLRESET_I N BUF G PLL_BASE Cmp_sys_clk_pll pllout_clk_sys (62.5 MHz) Clk_20m_vcxo_i Timing reference (125 MHz) xwr_core.vhd Entity: xwr_core clk_ref_i(0) clk_fb_i(0) clk_dmtd_i clk_ref_i phy_ref_clk_i wr_core.vhd Entity: wr_core phy_tx_clk ????.vhd Entity: xwr_softpll_ng clk_ref_i clk_sys_i clk_dmtd_i xwr_endpoint.vhd Entity: xwr_endpoint clk_sys_i BUF G clk_dmtd_i phy_ref_clk_i Gtp_bitslide.vhd Entity: gtp_bitslide rst_done_n rst_i IBUFDS_ GTE2 clk_125m_pllref_p_i clk_125m_pllref_n_i SoftPLL FMC DAC1 DAC2 VCXO 20MHz VCXO 25MHz CLK20_VCXO CDCM 61004 fpga_pll_ref_clk_123_p_i fpga_pll_ref_clk_123_n_i dac_dpll dac_hpll Clk_20m_vcxo_i PLL25DAC1_SYNC_N PLL25DAC_DIN PLL25DAC_SCLK PLL25DAC2_SYNC_N Next… implement “wr_gtx_phy_kintex7“ into White Rabbit PTP Core