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1 PIXEL H. Wieman HFT CDO LBNL 25-26-Feb-2008. 2 topics  Pixel specifications and parameters  Pixel silicon  Pixel Readout uSTAR telescope tests 

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Presentation on theme: "1 PIXEL H. Wieman HFT CDO LBNL 25-26-Feb-2008. 2 topics  Pixel specifications and parameters  Pixel silicon  Pixel Readout uSTAR telescope tests "— Presentation transcript:

1 1 PIXEL H. Wieman HFT CDO LBNL 25-26-Feb-2008

2 2 topics  Pixel specifications and parameters  Pixel silicon  Pixel Readout uSTAR telescope tests  Mechanical organization

3 3 Pixel geometry 2.5 cm radius 8 cm radius Inner layer Outer layer End view One of two half cylinders 20 cm  coverage +-1 total 40 ladders

4 4 Some pixel features and specifications Pointing resolution(13  19GeV/p  c)  m LayersLayer 1 at 2.5 cm radius Layer 2 at 8 cm radius Pixel size30  m X 30  m Hit resolution10  m rms Position stability6  m (20  m envelope) Radiation thickness per layer X/X0 = 0.28% Number of pixels164 M Integration time (affects pileup) 0.2 ms Radiation tolerance300 kRad Rapid installation and replacement Reproducible positioning

5 5 Silicon program pixel chips (MAPS) produced by IReS/LEPSI  IPHC (Strasburg) M. Winter C. Hu C. Colledani W. Dulinski A. Himmi A. Shabetai M. Szelezniak I. Valin

6 6 MAPS Properties: Signal created in low-doped epitaxial layer (typically ~10-15 μm) Sensor and signal processing integrated in the same silicon wafer Standard commercial CMOS technology

7 7 IPHC Functional Sensor Development Data Processing in RDO and on chip by generation of sensor. The RDO system design evolves with the sensor generation. 30 x 30 µm pixels CMOS technology Full Reticule = 640 x 640 pixel array Mimostar 2 => full functionality 1/25 reticule, 1.7 µs integration time (1 frame@50 MHz clk), analog output. (in hand and tested) All sensor families: Phase-1 and Ultimate sensors => digital output (in development) Leo Greiner

8 8 Grzegorz Deptuch MIMOSTAR 2/3 technology

9 9 Phase 1 / Ultimate technology (MIMOSA8/16/22)

10 10 IHCP Marc Winter et al Preliminary tests in Saclay of chips with 20 µm and 14 µm thick epitaxy layer Fe55 tests Noise and Fixed pattern noise measured In beam MIP detection efficiency measured with silicon strip telescope

11 11 IHCP Marc Winter et al

12 12 IHCP Marc Winter et al

13 13 Silicon summary, development of STAR pixels  Finished MIMOSTAR 2 with readout development  Working on MIMOSTAR 3 studies  Fab Phase 1 based on MIMOSA16/22 technology (digital output, no zero suppression)  Fab Ulitimate based on MIMOSA16/22 and SUZE technology (digital with zero suppression)  Issues  MIMOSTAR 3 yield  Radiation hardness (bulk damage) uReduce temperature uInvestigate silicon improvements

14 14 Readout system LBNL Leo Greiner Xiangming Sun Michal Szelezniak Thorsten Stezelberger Chinh Vu Howard Matis

15 15 System Design – System Blocks  This is a highly parallel system – a schematic representation is shown below.

16 16 1 m – Low mass twisted pair 6 m - twisted pair System Design – Physical Layout Sensors, Ladders, Carriers (interaction point) LU Protected Regulators, Mass cable termination RDO Boards DAQ PCs Magnet Pole Face (Low Rad Area ?) DAQ Room Power Supplies Platform 30 m 100 m - Fiber optic cables Leo Greiner

17 17 Detailed System Structure – Sensors and Cables Early prototype cable with 40 differential pair output, clock and control routed under sensor area. 4 LVDS outputs / sensor Cable 4 layer - 150 micron thickness Aluminum Conductor Radiation Length ~ 0.1 % 40 LVDS pair signal traces Clock, JTAG, sync, marker Fine twisted pair cables 125 micron diameter wire Soldered directly to cable Low stiffness / mass

18 18 RDO Board(s) New motherboard Two board System – Virtex-5 Development board mated to a new HFT motherboard Xilinx Virtex-5 Development Board Digital I/O LVDS Drivers 4 X >80 MHz ADCs PMC connectors for SIU Cypress USB chipset SODIMM Memory slot Serial interface Trigger / Control input FF1760 Package 800 – 1200 I/O pins 4.6 – 10.4 Mb block RAM 550 MHz internal clock Note – This board is designed for development and testing. Not all features will be loaded for production. Leo Greiner

19 19 Detailed System Structure – RDO Functional Data Path – Phase 1

20 20 Detailed System Structure – RDO Functional Data Path – Ultimate

21 21 Detailed System Structure – System Level Functioning

22 22 Data Rates - Parameters  2.5 hits / cluster.  1 kHz average event rate.  10 inner ladders, 30 outer ladders.  No run length encoding. 246248 X 10 27 295293 X 10 27 R = 2.5 R = 8.0 200 us 640 us Integration Time Radius Leo Greiner L

23 23 Data Rates  Ultimate => 49.7 MB / s raw addresses.  Phase–1 => 59.6 MB / s raw addresses The dead-time is primarily limited by the number of externally allocated readout buffers!

24 24 Prototype test in STAR with 3 Sensor Telescope Our goal was to test functionality of a prototype MIMOSTAR2 detector in the environment at STAR in the 2006-2007 run at STAR. We obtained information on:  Charged particle environment near the interaction region in STAR.  Performance of our cluster finding algorithm.  Performance of the MIMOSTAR2 sensors.  Functionality of our tested interfaces to the other STAR subsystems.  Performance of our hardware / firmware as a system.  The noise environment in the area in which we expect to put the final PIXEL detector. Stack of 3 MIMOSTAR2 pixel chips, Chip dimension: 4 mm X 4mm, 128 X 128 pixels

25 25 Telescope Infrastructure at STAR Magnet Pole Tip Insertion tube Electronics Box Beam Pipe

26 26 On the fly cluster finding first used with MIMOSTAR analog chips

27 27 Telescope DAQ

28 28 Distribution of track angles in Mimostar2 telescope Xiangming Sun Michal Szelezniak

29 29 Summary of 2007 Au + Au test in STAR  Integrated background small compared to real interaction signals  No noise pickup  Hit rate as expected  Readout system worked well in the STAR trigger DAQ environment  Cluster finding system worked well

30 30 Mechanical Program  Eric Anderssen, LBNL engineer working on ATLAS pixels is phasing into our pixel program – full time in April 2008 (carbon composite expert)  Contracted ARES company for analysis on cooling, precision mount design and refinement of ladder stability. uPhone meetings weekly uFirst stage report due in January

31 31 HFT Mechanical requirements Full self consistent spatial mapping prior to installation Installation and removal does not disturb mapping Rapid replacement 10 Micron stability (mapping of BarBar with visual coordinate machine)

32 32 Rapid installation while preserving spatial map

33 33 Summary  Silicon design and development carried out by IHCP uadditional testing at LBNL  Readout system with STAR integration, well advanced, LBNL  Mechanical work uProject engineer: Eric Anderssen LBNL uConsulting work: ARES corporation, Los Alamos branch

34 34 Next slide backup

35 35 yearly dose numbers  Au + Au  RHIC II luminosity: 7X10 27 1/(cm 2 sec)  Weeks per year operation: 25  Fraction of up time: 60%  radius: 2.5 cm upion dose: 73 kRad uUPC electron dose: 82 kRad uTotal dose: 155 kRad uTLD measured projection: 300 kRad  radius: 8 cm upion dose: 7 kRad uUPC electron dose: 2 kRad uTotal dose: 9 kRad uTLD measured projection: 29 kRad


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