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Processor Level Parallelism 1
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Parallelism Levels Levels we can attack parallelism:
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Bit Level Parallelism Circuits process bits in parallel
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Instruction Level Parallelism
Organization level may process instructions in parallel
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Higher levels Thread Level Task Level Application Level
Ability to run multiple simultaneous streams of instrucions Task Level Ability to run parts of a program on different chips Application Level Run separate jobs on different machines
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Process vs Thread Process : Program Own memory space
Has at least one thread
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Multi Tasking Multitasking
Done on single cores running multiple programs OS handles switch "Large" chunks of time Flush cache on switch
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Process vs Thread Thread : Instruction sequence Own registers/stack
Share memory with other threads in process
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Threaded Code Demo…
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Resource Usage Four threads running in 4-wide pipeline
Can't always fill all 4 issue slots Have bubbles from memory access, page faults, etc… Issue Slots
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Multithreading Multithreading
Alternate or combine threads to maximize use of processor Finer timescale Maintain cache Hardware required Multiple register sets Track "owner" of pipeline instructions
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Multithreading Corse Grained Multitasking
Threads run for number of cycles Must drain pipeline before switch
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Multithreading Single Pipeline Course Grained
Assumption 1 cycle to retire after stall Threads to run Single Pipeline Time
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Multithreading Dual Pipeline Course Grained
Assumption 1 cycle to retire after stall Threads to run Dual Pipeline Time
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Latency vs Throughput Multithreading favors throughput over latency
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Multithreading Fine Grained Multitasking
Hardware can switch to a new thread each cycle without draining pipeline
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Multithreading Single Pipeline Fine Grained
Assumption: Switches every cycle Threads to run Single Pipeline Time
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Multithreading Dual Pipeline Fine Grained
Assumption: Switches every cycle Threads to run Dual Pipeline Time
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SMT SMT : Simultaneous Multithreading
AKA Hyperthreading Issue ops from multiple threads in one cycle Time
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Multithreading SMT Try to start next thread early if spare pipeline
Threads to run C gets to jump in early as B2 not ready Time
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Multithreading SMT Otherwise switch like fine grained Threads to run
C gets full turn, A up next Time
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Multithreading SMT Still constrained by load delays Threads to run
C5, B3 not ready until 8; A7 not ready until 9 Time
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SMT Challenges Resources must be duplicated or split
Split too thin hurts performance… Duplicate everything and you aren't maximizing use of hardware…
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Intel vs AMD Variations on SMT
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Processor Level Parallelism Styles
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Processor Parallelism
Process Parallelism : Run multiple instruction streams simultaneously
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Flynn's Taxonomy Categorization of architectures based on
Number of simultaneous instructions Number of simultaneous data items
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Flynn's Taxonomy Categorization of architectures based on
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SISD SISD : Single Instruction – Single Data
One instruction One piece data May be pipelined or superscalar
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SISD SIMD : Single Instruction – Multiple Data
One instruction Multiple pieces of data
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SIMD Roots ILLIAC IV One instruction issued to 64 processing units
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SIMD Roots Cray I Vector processor
One instruction applied to all elements of vector register
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Modern SIMD x86 Processors SSE Units : Streaming SIMD Execution
Operate on special 128 bit registers 4 32bit chunks 2 64bit chunks 16 8 bit chiunks …
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MISD MISD : Multiple Instruction – Single Data
One piece of data Processed by multiple instructions Rare Space shuttle : Five processors handle fly by wire input, vote
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MIMD MIMD : Multiple Instruction – Multiple Data
Multiple pieces of data, multiple instruction streams
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MIMD MIMD : Multiple Instruction – Multiple Data Multi core processors
Super computers Computational Grids
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Coupling and Topologies
MIMD differences How connected are nodes? How shared is memory?
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BlueGene
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BG/P Full system : 72 x 32 x 32 torus of nodes
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COW Cluster of Workstations
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