1. FPGA Helix Tracking Algorithm for PANDA Yutie Liang, Martin Galuska, Thomas Geßler, Jifeng Hu, Wolfgang Kühn, Jens Sören Lange, David Münchow, Björn Spruck, Milan Wagner II. Physikalisches Institut, JUSTUS-LIEBIG-UNIVERSITÄT GIESSEN 31.03.2014

2. 2 Outline 1. Introduction to the PANDA Straw Tube Tracker (STT) 2. Road finding and momentum calculation 3. Performance study with C++ 4. Implementation with VHDL 5. Summary and outlook

3. 3 Straw Tube Tracker(STT)  4636 Straw tubes  23-27 planar layers 15-19 axial layers(green) in beam direction 4 stereo double-layers for 3D reconstruction, with ±2.89 skew angle(blue/red) From STT : Wire position + drift time

4. 4 Road Finding Hit Tube_ID Layer_ID Hit: Seg_ID(3 bits) + LayerID(4 bits) + Tube_ID (6 bits) + Arrival time 1: Start from inner layer 2: Attach neighbour hit to tracklet layer by layer Boundary between two segments. Number of neighbor: 2  4

5. x y Known : x i, y i, r i Question: To determine a circle, x 2 + y 2 + ax + by + c = 0 Method: Minimize the equation E 2 = ∑(x i 2 + y i 2 + a x i + b y i + c) 2 (1/di) 2 S x = ∑x i … S xx = ∑x i x i … S xxx = ∑x i x i x i … Calculation of circle parameters 5 1) Circle para. 2) Track quality.

6. To Improve the Momentum Resolution -- using a 2 nd iteration x y x c, y c, R Pt(input) 1 st iteration 2 nd iteration 0.2GeV/c : 0.195 ±0.0068 0.195±0.0068 0.5GeV/c : 0.5 ±0.0212 0.5 ± 0.0164 1.0GeV/c : 0.99 ±0.0595 1.0 ± 0.0317 2.0GeV/c : 1.85 ±0.213 2.0 ± 0.073 6 Pt(GeV/c) 1 st iteration2 nd iteration

7. Multi-track 7 Performance Study -- single/multi-track x(cm) y(cm) x(cm) y(cm) Single track, 0.2GeV

8. 8 20 MHz 2000 ns revolution time 200 ns gap  T Mean between 2 events: 50 ns  Drift time: ~200 ns Event Structure -- pile-up Wrong T0  Wrong drift circle  bad track quality Event pile-up

9. Event #4 Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) T 0 information: current event(Red) or other events(Green) 9 Performance study -- Dpm events, time-based

10.  15 GeV/c DPM events with 50 ns mean time  Input: STT Timestamps and Straw numbers (220 ns window)  Running t 0i window  Color code of isochrone: Black: Isochrone too large Red: Isochrone too small Green: Isochrone  Color code in upper panel:  Black: Hit position in timestamp  Red: t 0 from MC truth  Blue: Running χ 2 of tracking 10 Hitstream and tracking Display

11. 11

12. 1: Number of hits in the track 2: χ 2 of the track Assign a track to the correct event 12 χ2χ2

13. Event #1 Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) T 0 information: current event(Red) or other events(Green) 13 Assign a track to the correct event

14. Event #2 Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) T 0 information: current event(Red) or other events(Green) 14 Assign a track to the correct event

15. Event #3 Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) T 0 information: current event(Red) or other events(Green) 15 Assign a track to the correct event

16. Event #4 Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) T 0 information: current event(Red) or other events(Green) Assign a track to the correct event

17. VHDL implementation 2D Mapping Hit ToT T0 Ring Buffer Input Interface T0 Tracking module 5 4 8 6 7 2 3 1.. 9 Calc Mom Form tracklet Index 17

18. Hit ToT T0 T0+200 Tube_ID Layer_ID Initialization of the 2D Map 18

19. 19 PC as data source and receiver.  Ethernet.  Optical link (UDP by Grzegorz Korcyl ) (not integrated yet) FPGA FIFO Tracking algorithm Ethernet via Optical Link Setup and Test FIFO

20. Performance at FPGA 20 2: Timing Expectation: For event with 4 tracks : 200 cc+300 cc  300 to 500 cc (clock cycle)  3 to 5 μs/event, Agrees to the test with 1M events. Only 1 st iteration is implemented in VHDL 1: Device Utilization Summary:

21. 21 Summary and Outlook  2D map is used in road finding. Boundary between two segments. Four neighbour hits considered.  Momentum and χ 2 calculated.  Momentum resolution ~6%(1 st iteration)  ~3% (2 nd iteration). Next to do:  Study on the disentangle of pile-up event  Include MVD points

22. 22 Thank you

24. Performance study -- Dpm events, time-based Event #1 Black dashed line: track by MC truth Red line: recon. track Blue: recon. using outer layers drift circles belong to current event (Red) or other events (Green) T 0 information: current event(Red) or other events(Green) 24

26. VHDL implementation 1: Road finding: Using status machine to control the following procedures. 1)Hit sorting: fill hit into array_layer_id according to layer ID 2)Combine hits from two adjacent layers 3)Form a tracklet by attaching hit layer by layer tracklet_inner : layer 0-7 tracklet_outer: layer 8-15 4) Combine tracklet_inner and tracklet_outer. For one event with 100 hits (6 tracks): 1) 100 clock cycles (cc) 2) ~ 300-600cc 3) ~200cc  several us (if FPGA running at 100MHz) 26

27. xi yi xi_1cc  xx xx_1cc  xxx Sxxx += xxx_1cc a = Syy*(-Sxxx-Sxyy) - Sxy*(-Sxxy-Syyy);  yy yy_1cc Syy+=yy_1cc Syy_1cc  Syy*Sxxx 27 VHDL implementation 2: Momentum calculation 3: χ 2 calculation 24X24 bit not precise enough  32X32 bit

28. 28 PC as data source and receiver.  Ethernet.  Optical link (UDP by Grzegorz Korcyl ) (not integrated yet) FPGA FIFO Tracking algorithm Ethernet via Optical Link Setup and test FIFO

29. Simulation with ISim and test at FPGA 29 Track #1 #2 #3 #4 Xr (cm): -38.8 63.9 62.4 124.2 Yr (cm): -158.7 -129.9 -127.8 107.1 R(cm): 163.3 144.7 142.2 164.0 χ 2 : 0.40 0.63 0.58 0.74 Timing Expectation(4 tracks per event): 200cc+300cc  300~500cc  3~5 us/event, agrees to the test with 1M events.

30. 30

31. Device utilization Summary 31

32. PANDA@20MHz. 2*10 7 events/second 1 event: ~3 tracks/event * ~16 hits/track * ~ 2 (overlap factor)  ~100 hits/event When dividing STT into 16 layers, ~6 hits/layers. 6*6*15 = 540 combinations ~1~2 clock cycles/combination.  500~1000 clock cycles/event If FPGA running at 100MHz, (500~1000)*10ns/ 50ns  100~200 FPGA  25~50 CN

33. 0.2GeV 0.5GeV 2GeV1GeV 33 Performance study – single track x(cm) y(cm) x(cm) y(cm) x(cm) y(cm) x(cm) y(cm)

34. DPM background – Event # 1

35. To improve the momentum resolution x y x c, y c, R 0.2GeV/c : 0.195 ±0.0068 0.195±0.0068 0.5GeV/c : 0.5 ±0.0212 0.5 ± 0.0164 1.0GeV/c : 0.99 ±0.0595 1.0 ± 0.0317 2.0GeV/c : 1.85 ±0.213 2.0 ± 0.073 35 Pt(GeV/c)

36. 2**(-16) = 0.00001526