1. Presenter: Yi-Ting Chung Fast and Scalable Hybrid Functional Verification and Debug with Dynamically Reconfigurable Co- simulation

2. Abstract Hybrid functional verification & debug system – Combine emulator and simulator – Pros: (emulator) high execution speed + (simulator) full observability and controllability – Cons: simulator cannot handle too large designs This paper presents a scalable hybrid system – Based on dynamically reconfigurable co-simulation – Logic blocks can be dynamically relocated between simulator and emulator without recompilation

3. Hybrid Design Compilation Designer has to tag the logic blocks that are likely to be investigated HDL netlist HDL netlist FPGA based emulatorHDL simulator Partition the design into FPGA and perform logic optimization, and generate configuration bitstreams. When the TLB is moved to simulator, the input and output cross nets are synchronized between simulator and emulator. Simulator Prepare simulation libraries and testbench wrapper for TLBs

4. Hybrid Verification Flow Pure emulation: (Simulator is idle) – Design under test (DUT) is executed at hardware speed with massive sets of input stimuli for large number of clock cycles. – Checkpoints are saved periodically in verification controller (VC). On error detection: – VC reconfigures the system as a co-simulator. – The system is restored to the last stable checkpoint. – Designer selects a block under debug (BUD), and then VC transfers it to simulator. – If cause of error is not found, change a BUD, or trace back to previous checkpoints. rollback

5. Hybrid Verification Framework Interface to simulator Interface to emulator Input stimuli comes from 1.Hardware target 2.Software testbench In co-simulation, PIs are driven by simulator Synchronize cross nets values between simulator and emulator TLB Save values of FFs/memories/PIs. Period should > most error latency

6. Experimental Results 3 large SoC designs: Checkpoint period = 20K cycles. Bug detection: # TLB: 6 5 N = number of rollbacks Can handle individual BUDs although it cannot load the entire DUT for debug. Most of the errors (~80-90%) are traced using only 1 or 2 rollbacks, indicating that the checkpoint period is longer than the latency of most of the errors. How to select TLB?

7. Conclusion The paper offers a intuitive, flexible and efficient functional verification and debug methodology, with a completely scalable architecture for growing design size and complexity. The proposed system fully utilizes the advantages of both simulation and emulation technologies. The novel co-simulation strategy based on dynamic reconfiguration speeds up functional debug by eliminating the need for costly design recompilations whenever a logic block is relocated from emulator to simulator or vice versa.