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EE552 Extra Credit Project1 Extended Burst Mode Design Orignally Submitted by : Amish Patel Revised by : Sumit Bhargava

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Presentation on theme: "EE552 Extra Credit Project1 Extended Burst Mode Design Orignally Submitted by : Amish Patel Revised by : Sumit Bhargava"— Presentation transcript:

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2 EE552 Extra Credit Project1 Extended Burst Mode Design Orignally Submitted by : Amish Patel amishjpa@usc.edu Revised by : Sumit Bhargava sumitbha@usc.edu

3 EE552 Extra Credit Project2 Introduction Illustrate example on Extended Burst Mode Design

4 EE552 Extra Credit Project3 Topics of Discussion Extended Burst Mode Specification Hazard-free Next State Logic Synthesis 3D Automatic Synthesis Algorithm

5 EE552 Extra Credit Project4 Extended Burst Mode Specification All input transitions in input burst should change in assigned time d  Circuit settle with in time e  Output burst generated Arrivals of input transitions in input burst may be arbitrary order. Restrictions: Maximal Set property Unique Entry Condition

6 EE552 Extra Credit Project5 Restrictions Maximal set property --- to prevent non-deterministic state transitions 0 31 a-/ 2 c-/x- b+c-/y+ a+c+/x+ If c goes lower first in state 1  arbitrary decision to wait for b+ (go to state 2) or go to state 3 ? ? 0 31 a-/ 2 a+c-/x- c+/x+ b+c-/y+ Correct Implementation a, b and c are input variables, x and y are output variables + represents rising transition - represents falling transition Illegal implementationLegal implementation

7 EE552 Extra Credit Project6 Restrictions (Contd.) Unique entry condition 1 23 a+c+/y- a-/x+y+ 0 b+c*/x+ c-/x- abc/xy = 000/01 { 010/11,011/11 } {01011} Not Unique Correct 1 23 a+c+/y- a-c*/x+y+ 0 b+c*/x+ c-/x- abcxy=00001 { 01x11 } {11000} Unique

8 EE552 Extra Credit Project7 3D Machine Operation Mode I : input burst  output and sstate bursts simultaneously Mode II: input burst  output burst  sstate burst We will be using this mode in rest of presentation Mode III : input burst  sstate burst  output burst Three protocols / modes of operation differ in timing of burst of variable change

9 EE552 Extra Credit Project8 * = Directed Don’t Care ? This symbol is used to model concurrent input /output transitions Variable is allowed to change before it is required. The input variable is allowed to change with output and state variable Eg. 123 a+ b* / x-b+ / x+ Here we allow input variable b to change while going from state 1 to state 2 but state 2 does not care about value of b, but it is in state 3 that we require b to be high. Input variable b is changing all across going from state 1 to state 3 concurrently with output and state variable.

10 EE552 Extra Credit Project9 0123 abc/xy=000/00 a+b*/x+y+ b+c+/x- c-/x+y- a-b-/x- Example Mode II: input burst  output burst  sstate burst Mode III : input burst  sstate burst  output burst abc/xy=1*0/11 abc/xy = 111/01 abc/xy=110/10

11 EE552 Extra Credit Project10 11 0111 01 11 Conflict during Table Construction 00 bc xyxy xy a = 0a = 1 0 00 01 11 10 00 01 11 10 0001111000011110 2 11 Conflict Mode II Machine 0123 abc/xy=000/00 a+b*/x+y+ b+c+/x- c-/x+y- a-b-/x- abc/xy=1*0/11 abc/xy = 111/01 abc/xy=110/10

12 EE552 Extra Credit Project11 0111 01 11 Next-state Table (before layer encoding) Layer A 10 0110 0110 00 11 0 bc xyxy a = 0 00011110 bc xyxy a = 1 00011110 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 bc xyxy a = 0 00011110 bc xyxy a = 1 00011110 2 3 Layer B Mode III Machine

13 EE552 Extra Credit Project12 Next-state Table (after layer encoding) 011 101011 101 011 110 101110 101110 000 11 0 bc xyxy a = 0 00011110 bc xyxy a = 1 00011110 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 bc xyxy a = 0 00011110 bc xyxy a = 1 00011110 2 3 q = 0 q = 1 Mode II Machine

14 EE552 Extra Credit Project13 00 11 0111 01 11 000011001010 110111 101100 00 01 11 10 xy abc 0 2 1 10 Conflict Conflict during Table Construction 1 Mode III Machine 0123 abc/xy=000/00 a+b*/x+y+ b+c+/x- c-/x+y- a-b-/x- abc/xy=1*0/11 abc/xy = 111/01 abc/xy=110/10

15 EE552 Extra Credit Project14 11 01 11 Layer A 10 0110 0110 00 11 0 bc a = 0 00011110 bc xyxy a = 1 00011110 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 bc a = 0 00011110 bc xyxy a = 1 00011110 2 3 Layer B Next-state Table (before layer encoding) Mode III Machine

16 EE552 Extra Credit Project15 011 101011 101 011 110 101110 101110 000 11 0 bc xyxy a = 0 00011110 bc xyxy a = 1 00011110 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 bc xyxy a = 0 00011110 bc xyxy a = 1 00011110 2 3 q = 0 q = 1 Next-state Table (after layer encoding) Mode III Machine

17 EE552 Extra Credit Project16 Automatic Synthesis Procedure Next State Assignment Layer Minimization Layer Encoding Combinational logic synthesis

18 EE552 Extra Credit Project17 Another Example 201 c+/y+ c+/x+ c-/x- c-/y- If d sampled at rising edge of clock c is 1, x follows the clock and rises to 1,y=0; Otherwise, y follows clock and x=0

19 EE552 Extra Credit Project18 Example Specification 00 01 00 1110 01 11 10 00 01 0 0 0 0 0 00 1110 01 11 10 0 000 11 1 c a K-map for x Next State Table 0110 01 00 10 dc xy 201 c+/y+ c+/x+ c-/x-c-/y- 2 1 00

20 EE552 Extra Credit Project19 State Graph d=1 d=0 c+ x+ d- d+ c- 1 2 3 After x+ and d = 1, machine waits in 1, d may fall freely, leading to 2. If next input is d+ c-, machine may change from 2  1  3, giving output as 1-0-1-0 which is a dynamic hazard

21 EE552 Extra Credit Project20 Modified State Graph After Adding a New Layer d=1 d=0 c+ p+ d- d+ c- x+ Solution: Add new layer and to move to it via a state burst before enabling i/p to change if next i/p is unconditional and enables o/p to fall

22 EE552 Extra Credit Project21 Partial Next-State Table 00 01 00 1110 01 11 10 00 dc xy 00 01 00 1110 01 11 10 dc xy p=0 p=1 00 1

23 EE552 Extra Credit Project22 Partial K-map 00 01 0 0 0 0 00 1110 01 11 10 00 dc 00 01 0 0 0 0 00 1110 01 11 10 11 dc 11 xy

24 EE552 Extra Credit Project23 Partial K-map for next p 00 01 0 0 0 0 00 1110 01 11 10 01 dc 00 01 0 0 0 0 00 1110 01 11 10 11 dc 11 xy

25 EE552 Extra Credit Project24 References Synthesis of Asynchronous Controllers for Heterogeneous Systems, Kenneth Yun, Ph.D Dissertation 1994 Automatic Synthesis of Extended Burst Mode Circuits:Part I-II, Kenneth Yun,David Dill EE552- Fall 2001 Lectures and Discussions

26 EE552 Extra Credit Project25 Policy "I alone revised this project. I received no help from anyone else. This material is not copied or paraphrased from any other source except where specifically indicated. I grant my permission for this project to be placed on the course homepage during future semesters. I understand that I could receive an F for the course retroactively, even after graduation, if this work is later found to be plagiarized.“ Submitted by Sumit Bhargava

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