1. The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – Lab2 Adders & Multiplexers Ritu Bajpai September 25, 2008

2. Half-Adder We will make the schematic of a half adder in S-Edit. Simulate the schematic using S-Edit and T- Edit. Verify that your design corresponds to following truth table of a half adder. XYSumCarry 0000 0110 1010 1101

3. Full-Adder Now using the half adder we will create a full adder (a module that adds 3 bits together). Verify that our schematic simulation corresponds to the truth table of full adder shown in next slide.

4. Truth Table of a full adder XYCinSumCout 00000 00110 01010 01101 10010 10101 11001 11111

5. Analysis and result Along with the truth table, include the Boolean equation for the sum and carry of a half and a full adder. Show (through waveform) propagation delay in the sum and the carry of a half adder. Report (in tabular form)propagation delays T PHL and T PLH and then the signal delay as an average of T PHL and T PLH. Which output has larger delay? Sum or carry? Can you say why?

6. Analysis and result Show (through waveform), propagation delay in the sum and the carry of a full adder. Report (in tabular form)propagation delays T PHL and T PLH and then the signal delay as an average of T PHL and T PLH. Which output has larger delay? Sum or carry? Is the delay greater than half adder now? If yes, why?

7. Multiplexers A multiplexer has n select lines, 2 n inputs and 1 output. The number represented by the select lines chooses one of the inputs to be placed on the output.

8. Multiplexers X1 X2 X3 X4 S1S2 O

9. Home work Build and test a 2x1 multiplexer and perform schematic simulation for part. Build a 4x1 multiplexer from your 2x1 multiplexer and test it. You will be using this 4x1 multiplexer module in the next lab!