1. Digital Circuits Design Chin-Sung Lin Eleanor Roosevelt High School

2. Digital Circuits Design From Logic Gates to Boolean Functions From Boolean Functions to Truth Tables From Truth Tables to Logic Gates (Sum-of-Products) Logic Circuits Simulation Properties of AND and OR Gates Properties of NAND and NOR Gates Digital Logic Circuits Implementation Digital Building Blocks

3. From Logic Gates to Boolean Functions

4. From Logic Gates to Boolean Functions

5. A + B OR

6. From Logic Gates to Boolean Functions Y = C (A + B) A + B AN D OR

7. From Logic Gates to Boolean Functions

8. A B AN D

9. From Logic Gates to Boolean Functions Y = C + A B A B OR AN D

10. From Logic Gates to Boolean Functions

11. A B AN D

12. From Logic Gates to Boolean Functions A B AN D C D

13. From Logic Gates to Boolean Functions Y = A B + C D A B OR AN D C D

14. From Logic Gates to Boolean Functions

15. Y = A B + C D A B OR AN D C D B C

16. From Logic Gates to Boolean Functions

17. Y = A B C + A B C + B C D A B C OR AN D B C A B C B C D

18. From Boolean Functions to Truth Tables

19. From Boolean Functions to Truth Tables Y = C + A B A B OR AN D

20. From Boolean Functions to Truth Tables Y = C + A B A B OR AN D ABCY

21. From Boolean Functions to Truth Tables Y = C + A B A B OR AN D ABCY 000 001 010 011 100 101 110 111

22. From Boolean Functions to Truth Tables Y = C + A B A B OR AN D ABCY 0000 0011 0100 0111 1000 1011 1101 1111

23. From Boolean Functions to Truth Tables Y = A B + C D

24. From Boolean Functions to Truth Tables Y = A B + C D ABCDY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B OR AN D C D

25. From Boolean Functions to Truth Tables Y = A B + C D ABCDY 00000 00010 00100 00111 01000 01010 01100 01111 10000 10010 10100 10111 11001 11011 11101 11111 A B OR AN D C D

26. From Boolean Functions to Truth Tables Y = A B + A B ABY 00 01 10 11

27. From Boolean Functions to Truth Tables Y = A B + A B ABY 000 011 101 110

28. From Boolean Functions to Truth Tables Y = A B C + A B C ABCY 000 001 010 011 100 101 110 111

29. From Boolean Functions to Truth Tables Y = A B C + A B C ABCY 0000 0010 0100 0111 1000 1011 1100 1110

30. From Boolean Functions to Truth Tables Y = A B C + A B C ABCY 000 001 010 011 100 101 110 111

31. From Boolean Functions to Truth Tables ABCY 0000 0010 0100 0110 1000 1011 1101 1110 Y = A B C + A B C

32. From Truth Tables to Logic Gates

33. From Truth Tables to Logic Gates (Sum of Products) ABY 000 011 101 110 Y = A B + A B Product Sum of Products (SOP)

34. From Truth Tables to Logic Gates (Sum of Products) ABCDY 00000 00010 00100 00111 01000 01010 01100 01111 10000 10010 10100 10111 11001 11011 11101 11111

35. Y = A B + C D ABCDY 00000 00010 00100 00111 01000 01010 01100 01111 10000 10010 10100 10111 11001 11011 11101 11111 A B OR AN D C D

36. From Truth Tables to Logic Gates (Sum of Products) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 Y = A B C + A B C + A B C + A B C + A B C

37. From Truth Tables to Logic Gates (Sum of Products) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 Y = C + A B Y = A B C + A B C + A B C + A B C + A B C Y = A B C + A B C + A B C + A B C + A B C + A B C Y = (A B C + A B C) + (A B C + A B C) + (A B C + A B C) Y = A C (B + B) + A B (C + C) + A C (B + B) Y = A C + A B + A C Y = A C + A C + A B Y = (A + A) C + A B A B OR AND

38. From Truth Tables to Logic Gates (Sum of Products) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 Y = A B C + A B C + A B C + A B C + A B C A B OR AND Y = C + A B Logic Simplification Is there a better way?

39. Logic Simplification (Karnaugh Map, K-Map)

40. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 00 01 11 10 AB C K-Map Karnaugh Map (K-Map) is a graphical tool for simplifying Boolean functions Coordinates of each cell are the input variables, which are ordered in Gray code to ensure that only one variable changes between adjacent cells Each cell represents a row in the truth table The number of cells is always a power of 2

41. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 00 01 11 10 AB C K-Map Load the cell values from the truth table

42. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 0001 0101 1111 1001 AB C K-Map Load the cell values from the truth table

43. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 0001 0101 1111 1001 AB C K-Map Load the cell values from the truth table Group adjacent cells with 1’s into pairs, quad, and octet (powers of 2)

44. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 0001 0101 1111 1001 AB C K-Map Load the cell values from the truth table Group adjacent cells with 1’s into pairs, quad, and octet (powers of 2)

45. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 0001 0101 1111 1001 AB C K-Map Load the cell values from the truth table Group adjacent cells with 1’s into pairs, quad, and octet (powers of 2) A cell can be grouped more than once All cells need to be grouped if possible Group cells around the outer edge of the map Find the sum of these groups

46. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 0001 0101 1111 1001 AB C K-Map

47. Logic Simplification (Karnaugh Map, K-Map) ABCY 0000 0011 0100 0111 1000 1011 1101 1111 01 0001 0101 1111 1001 AB C Y = A B + C A B OR AND K-Map

48. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00000 00010 00100 00111 01000 01010 01100 01111 10000 10010 10100 10111 11001 11011 11101 11111 00011110 00 01 11 10 AB CD K-Map

49. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00000 00010 00100 00111 01000 01010 01100 01111 10000 10010 10100 10111 11001 11011 11101 11111 00011110 000010 010010 111111 100010 AB CD K-Map Y = A B + C D A B OR AND C D

50. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00001 00010 00101 00110 01000 01011 01100 01111 10000 10010 10100 10110 11000 11011 11100 11111 00011110 00 01 11 10 AB CD K-Map

51. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00001 00010 00101 00110 01000 01011 01100 01111 10000 10010 10100 10110 11000 11011 11100 11111 00011110 001001 010110 110110 100000 AB CD K-Map Y = A B D + B D

52. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00000 00011 00100 00111 01001 01010 01101 01110 10000 10011 10101 10111 11001 11010 11101 11111 AB CD K-Map

53. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00000 00011 00100 00111 01001 01010 01101 01110 10000 10011 10101 10111 11001 11010 11101 11111 00011110 00 01 11 10 AB CD K-Map

54. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00000 00011 00100 00111 01001 01010 01101 01110 10000 10011 10101 10111 11001 11010 11101 11111 00011110 000110 011001 111011 100111 AB CD K-Map

55. Logic Simplification (Karnaugh Map, K-Map) ABCDY 00000 00011 00100 00111 01001 01010 01101 01110 10000 10011 10101 10111 11001 11010 11101 11111 00011110 000110 011001 111011 100111 AB CD K-Map Y = B D + B D + AC = (B  D) + AC

56. Properties of AND and OR Gates

57. Properties of AND Gates Enabl e XY 0X0 1XX Any zero input of AND gate will zero the output One of the inputs of AND gate can be used as Enable pin When Enable is ‘1’, Y = X When Enable is ‘0’, Y = 0 Enabl e XY 000 010 100 111

58. Properties of AND Gates SelectABY 0ABB 1ABA 2-to-1 Multiplexer Select pin used to enable one of the AND gates When Select is ‘1’, Y = A When Select is ‘0’, Y = B SelectABY 0000 0011 0100 0111 1000 1010 1101 1111

59. Properties of OR Gates DisableXY 0XX 1X1 Any ‘1’ input of OR gate will make the output equal to ‘1” One of the inputs of OR gate can be used as Disable pin When Disable is ‘1’, Y = 1 When Disable is ‘0’, Y = X DisableXY 000 011 101 111

60. Properties of NAND and NOR Gates

61. Any Boolean function can be implemented by a combination of AND, OR, or NOT functions. Any Boolean function can be implemented using only NAND gates. Any Boolean function can be implemented using only NOR gates.

62. Universal Property of NAND Gates Any Boolean function can be implemented using only NAND gates. OR NOT AND De Morgan’s laws NAND: x · y = x + y

63. Universal Property of NOR Gates Any Boolean function can be implemented using only NOR gates. OR NOT AND De Morgan’s laws NOR: x + y = x · y

64. Digital Logic Circuits Implementation

65. Half Adder

66. Half-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Half Adder Half Adder A B C S 0 1+ ) 1 0 0 0 1 1 10 10 00 01 A B C S A B C S A B C S A B C S

67. Half-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ABCS 00 01 10 11 Half Adder Half Adder A B C S

68. Half-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ABCS 00 01 10 11 Half Adder Half Adder A B C S

69. Half-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ABCS 0000 0101 1001 1110 Half Adder Half Adder A B C S

70. Half-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S = ~AB + A~B = A  B C = AB ABCS 0000 0101 1001 1110

71. Half-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Half Adder Half Adder A B C S

72. Full Adder

73. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + ) 1 1 1 0 1 0 1 0 00 0 0 0 1 1 11 1

74. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + ) 1 1 1 0 1 0 1 0 00 0 0 0 1 1 11 1

75. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + ) A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A3A3 B3B3 00 0 0 0 1 1 11 1

76. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + ) A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A3A3 B3B3 S0S0 S1S1 S2S2 S3S3 0 1 1 11 1

77. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + ) A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A3A3 B3B3 S0S0 S1S1 S2S2 S3S3 C in C i C o C o

78. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + ) A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A3A3 B3B3 S0S0 S1S1 S2S2 S3S3 C in C i C o C o

79. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + ) A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A3A3 B3B3 S0S0 S1S1 S2S2 S3S3 C i/o FA C i/o CiCi CoCo

80. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A3A3 B3B3 S0S0 S1S1 S2S2 S3S3 C i/o FA C i/o CiCi CoCo A B S FA CoCo CiCi Full Adder

81. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CiCi ABCoCo S A B S FA CoCo CiCi Full Adder

82. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CiCi ABCoCo S 000 001 010 011 100 101 110 111 A B S FA CoCo CiCi Full Adder

83. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CiCi ABCoCo S 00000 00101 01001 01110 10001 10110 11010 11111 A B S FA CoCo CiCi Full Adder

84. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CiCi ABCoCo S 00000 00101 01001 01110 10001 10110 11010 11111 C i A\B01 0000 0101 1111 1001 K-Map C o = AB + C i A + C i B Boolean Function

85. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C o = AB + C i A + C i B

86. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CiCi ABCoCo S 00000 00101 01001 01110 10001 10110 11010 11111 C i A\B01 0001 0110 1101 1010 K-Map S = ~C i ~AB + ~C i A~B + C i AB + C i ~A~B Boolean Function

87. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S = ~C i ~AB + ~C i A~B + C i AB + C i ~A~B

88. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S = ~C i ~AB + ~C i A~B + C i AB + C i ~A~B = ~C i (A  B) + C i ~(A  B) = C i  A  B

89. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A B S FA CoCo CiCi Full Adder

90. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A B S FA CoCo CiCi Full Adder

91. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A3A3 B3B3 S 3 FA CoCo CiCi 4-Bit Full Adder A2A2 B2B2 S 2 FA CoCo CiCi A1A1 B1B1 S 1 FA CoCo CiCi A0A0 B0B0 S 0 FA CoCo CiCi

92. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A3A3 B3B3 S 3 FA CoCo CiCi 4-Bit Full Adder A2A2 B2B2 S 2 FA CoCo CiCi A1A1 B1B1 S 1 FA CoCo CiCi A0A0 B0B0 S 0 FA CoCo CiCi 4-Bit Full Adder

93. Full-Adder Example Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4-Bit Full Adder

94. Logic Circuits Synthesis

96. Digital Building Blocks

97. Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1

98. Arithmetic Logic Unit (ALU) Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OPCODE Operands

99. Instruction Format Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1

100. Central Processing Unit (CPU) Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1

101. Central Processing Unit (CPU) Select A B Y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OPCODE Operands Program

102. Computational Thinking through Digital Hardware

103. Reflections on Lessons Binary number system has been adopted as the machine language (it can do everything the decimal system did). Digitization & quantization methods can convert all the real- world information into binary data. Digital computer hardware are made of millions/billions of switches (which have only binary states: 1 & 0). Logic gates (which are made of switches) form the basic building blocks of digital logic circuits. Logic circuits can perform arithmetic, logic, and data flow control functions on binary data. Building a “thinking machine” purely in hardware.

104. Q & A