1. T305: DIGITAL COMMUNICATIONS Arab Open University-Lebanon Tutorial 51 T305: Digital Communications Block II – Part I - Synchronous Digital Hierarchy

2. T305: DIGITAL COMMUNICATIONS 2 Arab Open University-Lebanon Tutorial 5 Topics of today’s session Topic 1: Introduction Topic 2: The Plesiochronous Digital Hierarchy Topic 3: Synchronous Digital Hierarchy - Transport Topic 4: Synchronous Digital Hierarchy – Building STM-1 Topic 5: Preparation for Next Tutorial

3. T305: DIGITAL COMMUNICATIONS 3 Arab Open University-Lebanon Tutorial 5 Topic I - Introduction

4. T305: DIGITAL COMMUNICATIONS 4 Arab Open University-Lebanon Tutorial 5 Topic I - Introduction The synchronous digital hierarchy (SDH) is a world- wide standard for a digital communication network. It can be understood within the context of the systems that went before it: the plesiochronous digital hierarchy (PDH) and frequency division multiplexing (FDM). The frequency division multiplexing (FDM) allows a number of signals that have a relatively small bandwidth to share a medium that has a much larger bandwidth. In the case of telephony the bandwidth required to carry a single telephone circuit is 4 kHz.

5. T305: DIGITAL COMMUNICATIONS 5 Arab Open University-Lebanon Tutorial 5 Topic I – Introduction (cont.) Fig. Frequency division Multiplexing.

6. T305: DIGITAL COMMUNICATIONS 6 Arab Open University-Lebanon Tutorial 5 Topic I – Introduction (cont.) As shown above six telephone circuits, each with a bandwidth of 4 kHz, can be multiplexed onto a single carrier (path) with a bandwidth of 24 kHz. The signal in each circuit is combined with a different carrier frequency (ƒc) to give a range of frequencies that span above ƒc by 4 kHz. Using different frequencies but exactly the same technique, to multiplex composite 24 kHz signals, with four new carriers, to form a higher-order signal with a bandwidth of 96 kHz.

7. T305: DIGITAL COMMUNICATIONS 7 Arab Open University-Lebanon Tutorial 5 Topic I – Introduction (cont.) The pulse code modulation PCM is a technique which transforms an analogue telephone circuit into a digital signal, and involves three consecutive processes, called sampling, quantization and encoding. For PCM, as currently used in the telephone network, 8 bits are used to encode each sample and the sampling rate is 8000 times per second (often expressed as 8 kHz).

8. T305: DIGITAL COMMUNICATIONS 8 Arab Open University-Lebanon Tutorial 5 Topic I – Introduction (cont.) Fig. Pulse code modulation.

9. T305: DIGITAL COMMUNICATIONS 9 Arab Open University-Lebanon Tutorial 5 Topic I – Introduction (cont.) PCM-encoded signals are multiplexed together, sample by sample, to form an aggregate signal which is called the primary signal. In Europe the standard primary signal is made up from 30 speech bytes, 1 signaling byte and 1 overhead byte. Each sequence of bytes is referred to as a frame and one frame is constructed every 125 μs, hence there are 8000 frames per second. PCM frames, multiplexed together to form a hierarchy of bit-rates called the plesiochronous digital hierarchy (PDH).

10. T305: DIGITAL COMMUNICATIONS 10 Arab Open University-Lebanon Tutorial 5 Topic II - The Plesiochronous Digital Hierarchy

11. T305: DIGITAL COMMUNICATIONS 11 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy Time division multiplexing The TDM principle is shown below, in which three input signals, or tributaries, of the same bit-rate are multiplexed together in two different ways to form a single signal with an aggregate bit-rate, equal to the sum of the three.

12. T305: DIGITAL COMMUNICATIONS 12 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Fig. Time division multiplexing.

13. T305: DIGITAL COMMUNICATIONS 13 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Following figure shows the multiplexing stages in the PDH hierarchy as a series of steps, where the ‘up’ steps are multiplexing signals together and the ‘down’ steps are de-multiplexing the same signals. There are three stages of multiplexing: from 2 to 8, 8 to 34 and 34 to 140 Mbit/s.

14. T305: DIGITAL COMMUNICATIONS 14 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Fig. PDH multiplexing stages.

15. T305: DIGITAL COMMUNICATIONS 15 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Each multiplexer has four input signals (tributaries) which are combined, together with overhead and control bits, to give a single bit-rate as shown on the right of each multiplexer (mux). All three stages use bit-interleaving. The signal shown entering the bottom of each box is the clock source at a specified nominal frequency. It can be seen that the bit-rate out of the multiplexer is greater than the sum of the bit-rates at the input. Additional bits, often referred to as ‘overhead’, need to be added to the combined signals to maintain bit synchronization and frame (or word) synchronization, two key principles of digital transmission.

16. T305: DIGITAL COMMUNICATIONS 16 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Bit synchronization is the requirement to ensure that the receiver can ‘read’ all the bits, and in the case of PDH this means that each multiplexing stage has to be able to cope with tributaries that have variations, within controlled limits, in their bit-rates. These variations are attributable to the fact that PDH uses separate clocks to time each multiplexer, a feature which is reflected in the ‘plesiochronous’ in PDH. Plesiochronous is taken to mean ‘nearly synchronous’. In PDH the variation in timing, between the tributaries, is handled by a process called justification which can add extra bits to match the bit-rate of each tributary to the aggregate bit-rate.

17. T305: DIGITAL COMMUNICATIONS 17 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Frame synchronization is concerned with marking structure within the bit-stream so that the receiver can identify the location of data blocks. A frame alignment word (FAW) is used to mark the beginning of every frame. Because of the justification bits, in particular their control information, are embedded into the digital signal, it is only possible to derive the original signal by passing the aggregate signal through a demultiplexer as shown below. It is necessary to provide an entire de-mux and mux chain at B, even when there is only one 2 Mbit/s path between A and C that needs to be de-multiplexed at B. In this way many 2 Mbit/s paths go up and down multiplex chains before finally reaching their destination – in this case C.

18. T305: DIGITAL COMMUNICATIONS 18 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Fig. PDH multiplex ‘mountain’. The burden of providing chains of multiplexers has been called the multiplex mountain problem. Before SDH this was becoming an important issue for telecommunications operators.

19. T305: DIGITAL COMMUNICATIONS 19 Arab Open University-Lebanon Tutorial 5 Topic II- The Plesiochronous Digital Hierarchy (cont.) Summary The primary signal in PDH is byte-interleaved. PCM has led to a standard frame of 125  s. Plesiochronous timing sources have led to complex justification processes. A frame alignment word is used to identify each frame. PDH is burdened with the ‘multiplex mountain’ problem.

20. T305: DIGITAL COMMUNICATIONS 20 Arab Open University-Lebanon Tutorial 5 Topic III - Synchronous Digital Hierarchy – Transport

21. T305: DIGITAL COMMUNICATIONS 21 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport Fig. STM-1 frame Structure. STM-1 Frame SDH has a relatively simple structure (STM-1 frame) organized around a 125  s frame as shown below.

22. T305: DIGITAL COMMUNICATIONS 22 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport (cont.) Each STM-1 (synchronous transport module) frame is represented as a single block 270 bytes wide and 9 bytes deep. In practice each frame is transmitted as a continuous sequence of bits, often called a bit-stream, with the last bit of one frame being immediately followed by the first bit of the next. The first 9 columns of the STM-1 are allocated as overhead. The remaining 261 columns are called the payload area and are used to carry the SDH containers. The representation of the STM-1 frame as a block allows us to see that the individual columns can be removed from, and inserted into, the frame without interfering with the other columns. As shown below, a single column can be extracted from the payload area.

23. T305: DIGITAL COMMUNICATIONS 23 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport (cont.) Fig. Accessing a column from the frame. The organization of the STM-1 frame has been specifically chosen to transport the full range of PDH bit-rates and provide sufficient flexibility to transport future services based around different bit-rates.

24. T305: DIGITAL COMMUNICATIONS 24 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport (cont.) All bit-rates must be supported in such a way that there is scope for mixing and matching; for example, a single STM-1 needs to be able to transport both 2 Mbit/s and 34 Mbit/s, and any bit-rate transported should be able to be inserted and dropped (add/drop) without de-multiplexing the entire STM-1. SDH is able to transport containers of different sizes by using different numbers of columns. Just as it is easy to conceive of extracting columns from the block representation, bytes can be extracted, or inserted, from a serial bit-stream by counting between each byte, where each byte in a column is separated by 270 bytes.

25. T305: DIGITAL COMMUNICATIONS 25 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport (cont.) Building transport The transmission of digital signals over optical fibre allows for transmission rates far in excess of the 155.52 Mbit/s defined as the aggregate rate for STM-1. STM-4 622.080 Mbit/s STM-16 2488.32 Mbit/s STM-64 9953.280 Mbit/s The block representation helps us to group together functions and this philosophy is extended to multiplexing to higher rates. Theoretically, STM-n signals can be constructed from n  155 Mbit/s by byte-interleaving.

26. T305: DIGITAL COMMUNICATIONS 26 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport (cont.) Fig. Byte-interleaving of STM-1s into STM-n.

27. T305: DIGITAL COMMUNICATIONS 27 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport (cont.) Figure (a) shows a hypothetical SDH module, conceptual transport module (CTM). Each square in the figure is a byte, and the diagram shows how three CTM-1s are combined into a CTM-3 using byte- interleaving. The three-dimensional representation is used in (b) where sixteen STM-1s have been byte-interleaved into an STM-16. The format of the STM-1 signal is such that when higher- rate modules (STM-n) are constructed, using byte- interleaving, there is no loss of the shape that has been built into the STM-1 block representation. Byte-interleaving results in the STM-16 signal having an aggregate bit-rate which is exactly 16 times that of a single STM-1.

28. T305: DIGITAL COMMUNICATIONS 28 Arab Open University-Lebanon Tutorial 5 Topic III- Synchronous Digital Hierarchy – Transport (cont.) Summary An STM-1 frame can be represented as a 270 column by 9 row block. An important distinction is drawn between overhead and payload. SDH uses a frame period of 125  s. A column can be easily identified within an STM-1. Accessing of columns provides SDH with an add/drop capability. An STM-n signal can be seen as n byte-interleaved STM-1s.

29. T305: DIGITAL COMMUNICATIONS 29 Arab Open University-Lebanon Tutorial 5 Topic IV - Synchronous Digital Hierarchy – Building STM-1

30. T305: DIGITAL COMMUNICATIONS 30 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 All containers have extra, overhead, bytes added to them to become virtual containers (VCs). Figure below shows the SDH multiplexing structure, which is based upon the International Telecommunication Union’s (ITU) definition. It is clear that each of the PDH bit- rates can be accommodated within 155 Mbit/s.

31. T305: DIGITAL COMMUNICATIONS 31 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Fig. SDH multiplexing structure.

32. T305: DIGITAL COMMUNICATIONS 32 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Multiplexing and mapping can be distinguished by the relationship of bytes before and after the process. The bytes in the mapped signal stay together, while those of multiplexed signals are interleaved. Aligning allows the start position of a virtual container to be varied within an administrative unit (AU) or tributary unit (TU). The size of the VC and AU/TU is the same, so unless the start position of the VC coincides exactly with the start of an AU/TU the VC will straddle the boundary of two consecutive AU/TU frames.

33. T305: DIGITAL COMMUNICATIONS 33 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Trace the path from the C-4 (container) to the STM-n, reading from right to left. The C-4 block, which is called a container because it ‘contains’ an entire 140 Mbit/s PDH frame, is mapped directly into the payload area of a VC-4. A container together with some overhead is called a virtual container. A VC is located within an administrative unit or a tributary unit, and the location is specified by a pointer value held within the AU or TU overhead. For example, the C-4 maps into the VC-4, which in turn is aligned into an AU-4. Many stages are involved in tracing out the path from C-12 to STM-1, a state that is reflected in the complexity of paths through the multiplexing structure. The variety of routes is to provide the maximum flexibility in transporting mixed payloads. For example, a single STM-1 may need to transport PDH rates of 1.5, 2 and 45 Mbit/s.

34. T305: DIGITAL COMMUNICATIONS 34 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Fig. Relationship of STM-1, AU-4 and VC-4. STM-1 – Looking at the payload

35. T305: DIGITAL COMMUNICATIONS 35 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) The STM-1 frame is the full 9 × 270 byte block. The AU-4 occupies all the payload area (9 × 261) plus row four of the overhead. The pointer address, which is located in row four of the overhead, is used to locate the start of the VC-4, which unlike the AU-4 does not have a fixed position within the STM-1. The floating (variable phase) nature of the virtual containers, together with the pointer mechanism, is one of the key features of SDH. The VC-4 occupies the whole payload area of the AU-4. Often the VC-4 will be used to hold lower-order virtual containers, and in this case part of the VC-4 payload area will be allocated to tributary unit (TU) pointers which will indicate the start position of lower-order VCs. This cascade effect provides the flexibility in payload size necessary to meet the demand of the services to be transported over SDH and is illustrated below.

36. T305: DIGITAL COMMUNICATIONS 36 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Fig. Pointing to cascaded payloads.

37. T305: DIGITAL COMMUNICATIONS 37 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) The AU-4 pointer marks the location, within the AU-4, where the VC-4 starts. TU pointers, which have a fixed position within the VC-4, similarly mark the start of lower-order VCs, in this case VC-12s. The cascading of pointers allows lower-order VCs to be located in an STM-1 frame, simply by encoding nested pointer addresses.

38. T305: DIGITAL COMMUNICATIONS 38 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) A closer look at overheads Overhead functionality can be classified into two types. The operation and maintenance of the SDH signal itself, and includes bytes that provide framing, identification and alarm indication, functions which are important for the transmission of signals. The second type includes error performance indication and data communications channels, which provide error performance monitoring and an embedded management communication channel.

39. T305: DIGITAL COMMUNICATIONS 39 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Fig. Paths and sections.

40. T305: DIGITAL COMMUNICATIONS 40 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Figure above shows a simple transmission system, made up of two multiplexers (mux) connected on an optical link containing three regenerators. If SDH is to carry out its transport function then it is necessary to send SDH signals to a distant location, a process that requires the logical signal to be converted to a physical signal. This function is carried out by the STM-n multiplexer.

41. T305: DIGITAL COMMUNICATIONS 41 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Signals are attenuated and distorted as they travel along the optical fiber. The regenerator detects the incoming optical signal and ‘regenerates’ a perfectly formed signal with the same information content. The distant STM-1 multiplexer receives the optical signal and reconverts it into a logical signal for processing. The link between two regenerators is called a regenerator section, between two STM-1 multiplexers a multiplex section, between two VC-4s a higher-order path, and between two VC- 12s a lower-order path.

42. T305: DIGITAL COMMUNICATIONS 42 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Section overhead As shown below, the overhead is grouped into two areas: the regenerator section overhead (RSOH) and the multiplex section overhead (MSOH). Not all the bytes in the overhead have been allocated a specific function. A1 and A2 bytes together contain a frame alignment word. This is a known sequence which allows the start of each STM-1 frame to be clearly identified. Frame alignment is critical to the multiplexing and de- multiplexing of the SDH hierarchy, as all of the pointers are predicated upon a known location within the STM-1 frame. For example, once the location of the frame is identified it is a simple matter of counting to find the AU pointer.

43. T305: DIGITAL COMMUNICATIONS 43 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) The frame alignment word is repeated with every frame to maintain alignment, and to allow the frame to be re-aligned. When STM-1 signals are multiplexed into an STM-4, then the C1 byte allows each STM-1 to be uniquely identified. This is necessary as each STM-1 will be using the same frame alignment sequence.

44. T305: DIGITAL COMMUNICATIONS 44 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Fig. Allocation of section overhead.

45. T305: DIGITAL COMMUNICATIONS 45 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) The B2 bytes provide an error monitoring capability, a function that is common to all sections and paths. Error monitoring provides a self-diagnostic capability and is seen as a significant benefit of SDH over PDH. In the STM-1 a 24-bit interleaved parity (BIP-24) signal is used for error monitoring. Data communication channels (DCCs) are another feature shared by paths and sections. In the STM-1 frame twelve bytes (D1 to D12), three in the RSOH and nine in the MSOH, are allocated to two DCC channels, which is intended to provide an embedded data communications link.

46. T305: DIGITAL COMMUNICATIONS 46 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Path overhead The VC-4 (higher-order path) contains 9 bytes, arranged in one column, dedicated to management and supervision of that path. If lower-order paths are contained within the VC-4 then they will have their own path overhead. For example, a VC-12 (lower-order path) will have 1 byte of overhead. The path overhead will stay with the path layer payload as it is transported across an SDH network and it will provide precise information on that path regardless of the number of networks, sub-networks or links it crosses.

47. T305: DIGITAL COMMUNICATIONS 47 Arab Open University-Lebanon Tutorial 5 Topic IV- Synchronous Digital Hierarchy – Building STM-1 (cont.) Summary Containers are defined for the PDH hierarchy and ATM. Overhead is added to a container to form a virtual container (VC). VCs define the path level and are the main transport mechanism. Multiplexing, mapping and aligning are all used in the SDH process. Administrative units (AUs) and tributary units (TUs) contain pointers that locate VCs within their payload areas. Overhead bytes are used for alarm information, error monitoring (BIP) and data communication (DCC).

48. T305: DIGITAL COMMUNICATIONS 48 Arab Open University-Lebanon Tutorial 5 Topic V - Preparation for Next Tutorial