1. CS 162 Discussion Section Week 6

2. Administrivia Project 2 Deadlines – Initial Design Due: 3/1 – Review Due: 3/5 – Code Due: 3/15

3. Project 2 Overview Part I – Implement file system calls – like create, open, read, write, close etc. Part II – Implement support for multiprogramming – Play with allocating memory, virtual memory Part III – Implement system calls – like exec, join and exit Part IV – Implement lottery scheduling

4. Recap Why do we have a virtual address space?

5. Recap How is a virtual address translated into a physical address?

6. Recap Why do we have multiple levels of page tables?

8. What is the size of the page table in a 64bit system if each page is 4K in size? – 16 PB How many levels would you need if you had 1024 entry page tables?

9. TLB Caching Applied to Address Translation

10. Caching caching is to store copies of data at places that can be accessed more quickly than accessing the original. Locality: – Temporal locality Example: recently accessed files – Spatial locality Example: ls command

11. Memory Hierarchy Image Source: http://www.sal.ksu.edu/faculty/tim/ossg/

12. Issues in Caching Cache Hit Cache Miss effective access time is defined with the following equation: T = P(cache hit)*(cost of hit) + P(cache miss)*(cost of miss)

13. Problem What is the effective access time for TLB with 80% hit rate, 20ns TLB access time and 100 ns Memory access time (assume two-level page table that is not in L2 cache)?

14. Is there any way to make the page table smaller?

15. Linear inverted page tables

16. Hashed inverted page table

18. Design Issues in Caching The design of a caching mechanism needs to answer the following questions: – How is a cache entry lookup performed? – If the data is not in the cache, which cache entry should be replaced? – How does the cache copy maintain consistency with the real version of data?

19. Types of Cache Direct Mapped Cache Fully Associative Cache N way Set Associative Cache

21. 2-Way Associative Cache in TLB