1. Mitglied der Helmholtz-Gemeinschaft Status of the MicroTCA developments for the PANDA MVD Harald Kleines, ZEL, Forschungszentrum Jülich

2. MicroTCA at the PANDA Multiplexing Layer Concentrator modules:  Receive data from detector front end  Send data to “Super burst builder” (locally or via central Uplink) Central Input for SODA, local distribution on Backplane  Radial clocks TCLA, TCLB or bussed clocks? Performance? CPU for management + control system + uplink for low data rate subsystems Still many open issues AMC: CPU AMC: Timing AMC: Con- centrator 1 AMC: Con- Centrator 2 AMC: Con- Centrator n MCH Backplane 4 Lane PCIe (Point-to-Point to MCH) Clocks, Triggers, Control Signals according to MTCA.4 („uTCA for Physics“) SODA Uplink MicroTCA Crate Optional local Uplinks

3. PANDA MVD Multiplexing Board (MMB) Pluggable into MicroTCA crate or Compute Node 3 or ATCA carrier SODA could be on the MMB, if backplane performance is not sufficient Details net yet fixed (FPGA-Type,….) 10 Gbit/s Uplink as a first approach, finally a higher multiplexing level is intended GBT-Protocol to Service Board or CERN board (Option) SODA via Backplane

4. Iterative Development of Lab Test Systems For TOPIX2  Dedicated Board  ML605 + “FMC-like” Adapterboard  SIS1100 readout For TOPIX3  Up to now just contribution to the FPGA code of IKP  Intended Mapping of GBT-Protocol to PCIe still missing For MicroTCA  Development of optical Uplink PC GBT Protocol GBT CERN Board TOPIX3 INFN Torino Board E-Link

5. Development of 10 Gb/s link FPGA: Xilinx XC5VLX30T with FF665 package, well known in ZEL Avoid 10 GigaBit/s on PCB (8B/10B-Coding => 12,5 GHz)  Use XAUI interface (4 * 2,5 GBit/s)  Use X2 transceiver Modul FTLX8541E2 Synchronization of Vertex5 MGT-Ports?  Avoid softcore  USE Parallel-to-XAUI SERDES: PM8358, well known from QPACE project In future: Use SFP+ tranceiver

6. PCIe board Status:  First prototype did not work because of hardware problems  Redesign has been finished  PCB of second prototype has arrived, components not yet mounted

7. MicroTCA Board for the 10G optical uplink Full Size (and Single Width) due to the big X2 transceiver Comparison to PCIe  Additional management, telecom clocks, GbE Option  Power supply more complex, less available space on PCB PCIe (4 Lanes) PIC32 I2CI2C div. Signals GbE (Option) XC5VLX30T T.CLOCK A,B PM8358 Finisar FTLX8541E2 SC-connector XAUI (4 x 3,125 Gbit/s) XGMII (32 Bit parallel)

8. Status of the MicroTCA board Has been produced Management under Test Some minor HW modifications already found

9. FPGA Firmware Option 1 „Bridge Functionality“  by transparent transmission of TLPs (Transaction Layer Packets) Definition of private link protocol using 64b/66b control characters for TLP framing, error reset, …… Tradeoffs: High latency, system crash by link removal, possible system blocking due to limited number of uncompleted transactions Problem: Virtex5 embedded PCIe endpoint does not support downstream ports  CPU in MicroTCA crate required  BIOS address mapping in MicroTCA crate must be known in PC system  Change to different FPGA

10. FPGA Firmware Option 2 DMA engine on PCIe board Commercial Solution: Northwest Logic DMA back-end core Dedicated sequencer on MicroTCA board that pushes data upstream to PC system Tradeoffs/Problems:  1,3 Mbit block RAM  PCIe latency to PC memory must be below 50 μs  Proprietary solution PCIe PC PCIe board Device Driver Application Software PCIe Endpoint DMA Engine Link Protocol Mapper

11. Kinex-7 Final “MVD Multiplexing Board”  Virtex-5 quite obsolete,  Virtex-6 will fade out, with broad availability of Xilinx series 7 FPGAs  Kintex-7 still not publically available,  Price tag for XC7K325-2FFG900 from digikey: ~1400$  Start GBT developments with Kinex 7  Acquired evaluation board KC705 with XC7K325-2FFG900,  FMC board with SFP+ cages (not yet delivered) and transceivers  GBT/PCIe development for several simultaneous ports  Responsible: Matthias Drochner