1. DESIGN OF LATERAL MOSFET IN SILICON CARBIDE
Mississippi State University
Department of Electrical and Computer Engineering

2. Design of Lateral MOSFET in Silicon Carbide
Abstract
Many silicon power MOSFETs have reached their limits. The blocking voltages, on-resistances and switching speeds are not efficient enough for the applications. A plan to use silicon carbide as the semiconductor material instead of silicon has yielded theoretical results that are much greater than that of silicon. In fact, the theoretical on-resistances of silicon carbide is 300 times lower than that of silicon, and the blocking voltages are ten times better in silicon carbide than in existing silicon devices. The only problem with this is that those theoretical limits of silicon carbide have not been efficiently obtainable nor reachable with existing designs. Also, the material development and design inhibits these theoretical values from being reached. Through simulation and research of existing models and designs, a lateral 6H-SiC silicon carbide power MOSFET will be designed in order to obtain a variety of blocking voltages and as well as efficient on-resistances, which will decrease the switching speed of the device. Other improvements will be incorporated into the design, such as new implant annealing methods and new layout methods. Also, the device’s physical size will be limited to 500 m X 500 m, which will help decrease the on-resistance of the device.

3. Team Members Elmer Durrell III Senior - Electrical Engineering
Design of Lateral MOSFET in Silicon Carbide
Team Members
Senior Design I
- Researched information on Power MOSFETs
- Researched information on epitaxial growth methods
- Performed epitaxial growth to determine process
- Project documentation
- Performed SRIM simulations
- Analyzed data from Medici simulations
- Project Website
- Team Page
- Timeline
- Updating Documents
- Determined standard device dimensions
- Created device drawings and cross-sections
- Determine device layers and resulting masks layers
- Worked on mask layout in Cadence
- Project presentations
Senior Design II
- Project Team Leader
- Helped with Project Website
- Recorded wafer appearance before and after Silane Anneal
- Helped extract sizes of single finger device
- Performed Blocking Voltage tests for device
- Speaker for final Design Review
Senior Design I
- Project Team Leader
- Researched information on Power MOSFETs
- Performed calculations for On-Resistance
- Performed calculations for Contact Resistance
- Project documentation
- Project presentations
- Project Website
- Title Page
- Abstract
- Updating Documents
- Speaker for Preliminary Design Review
- Speaker for Final Design Review
Senior Design II
- Helped extract size of single finger devices
- Helped with Project Website
- Performed Blocking Voltage tests for device
Senior Design I - Researched information on power MOSFETs - Project documentation - Researched Cadence design rules for layout Proofread project documentation - Assisted with web design - Project presentations Senior Design II - Researched topics on transmission line method (TLM) - Measured contact resistance using TLM MatLab analysis for contact resistance - Project presentations - Helped with Project Website - Proofread project documentation
Senior Design I
- Research of blocking voltage and associated concepts
- Research of on-resistance in lateral MOSFETs
- Research of contact resistance
- Project documentation
- Project presentations
- Analysis of Medici simulations
Senior Design II
- Project documentation updates
- Further research of Breakdown voltage in SiC devices
- Speaker for Preliminary Design Review
- Device testing
- Performed Blocking Voltage tests for device
Elmer Durrell III
Senior - Electrical Engineering
Janna Bonds Dufrene
Senior - Electrical Engineering
Dr. Jeffrey Casady
Faculty Advisor
Assistant Professor
Electrical Engineering
Mississippi State University
Wendy L. Evans
Senior - Electrical Engineering
Christopher R. Sanders
Senior - Electrical Engineering

4. Design of Lateral MOSFET in Silicon Carbide
High Temperature, High Voltage, and High Frequency through Silicon Carbide Technology Brings Dramatic Impacts on Smart Power Applications
Military
Silicon Carbide
MOSFET
Commercial
Higher Breakdown Voltage
Lower On-Resistance
Consumer

5. Design Requirements Epitaxial Layer Growth Fabrication Process
Design of Lateral MOSFET in Silicon Carbide
Epitaxial Layer Growth
Develop and design a repeatable process to grow p-type epitaxy with the dopant concentration between the range of 5e15 cm-3 to 1e16 cm-3.
Fabrication Process
Complete process traveler for the MOSFET fabrication sequence to be executed by the SiC fabrication foundry.
Device Layout
Layout masks used for fabrication of the MOSFETs using Cadence tools, following closely the outlined design constraints.
Blocking Voltage
Devices will be designed to achieve blocking voltages of 600V, 1200V and 1800V.

6. Design Requirements On-Resistance Contact Resistance Physical Size
Design of Lateral MOSFET in Silicon Carbide
On-Resistance
Devices will be designed to have on-resistances of 50mohm-cm2, 350mohm-cm2 and 2450mohm-cm2, for 600V, 1200V and 1800V, respectively.
Contact Resistance
Achieve contact resistance of approximately 1 m - cm2
Physical Size
Total active area of device will be no larger than 500 m x 500 m.
Cost
Estimated cost to produce and manufacture the set of masks will be approximately $4,000, and four wafers with epi layers will cost approximately $6,000.

7. DEVICE SPECIFICATIONS SIMULATION SPECIFICATIONS
Design of Lateral MOSFET in Silicon Carbide
Test Specification
Physical Size
Electric Field
Contact Resistance
On-Resistance
Blocking Voltage
Device Layout
Fab Process
Threshold Voltage
PROBE STATION
CADENCE
2-D MEDICI TESTING
2-D SRIM TESTING
1-D EXCEL TESTING
REQUIREMENTS
DEVICE SPECIFICATIONS
SIMULATION SPECIFICATIONS            

8. Breakdown Voltage Point A Point B
Design of Lateral MOSFET in Silicon Carbide
Breakdown Voltage
Point A
Point B
To achieve the minimum degree of breakdown in the gate oxide and silicon carbide, doping was set to
Point B - Breakdown of silicon
carbide due to low
doping in the drift layer.
Point A - Breakdown of oxide
due to high doping
in the drift layer and
electric field in the gate
oxide.
2.8E+17 cm-3 in the drift layer
4.6E+15 cm-3 in the inversion layer

9. On - Resistance Point A Point C Point B
Design of Lateral MOSFET in Silicon Carbide
On - Resistance
Point A
Point C - Channel Resistance - Control doping in inversion layer to limit on-resistance
Point C
Point A - Drain and Source Resistances - Control doping
in the n+ drain and source regions to limit on-resistance
To achieve the minimum degree of on-resistance in the device doping was set to
2.8E+17 cm-3 in the drift layer
Point B
Point B - Diffusion Resistance - Control doping in diffusion layer to limit on-resistance
4.6E+15 cm-3 in the inversion layer
1E+19 cm-3 in the source and drain implant regions

10. Design of Lateral MOSFET in Silicon Carbide
Device Layout
Device Layout in Cadence showing size of largest single finger device, which is 83 um x 175 um.
Device Layout showing cross-section and lengths (LDR - drift region length, LDFO - drain overlap of field oxide, LPFO - poly overlap of field oxide)

11. Device Layout in Cadence
Design of Lateral MOSFET in Silicon Carbide
Device Layout in Cadence
Die:
a cell which contains all the devices to be fabricated
arrayed in a pattern to cover a circular region with a 50 mm diameter
Die size: 5 mm x 5mm
Die contains:
20 single finger devices
12 ten finger devices
4 twenty finger devices
Various test structures
Alignment marks

12. Device Implementation
Design of Lateral MOSFET in Silicon Carbide
Device Implementation
Mask 5: Gate Metal
Mask 7: Gate Contact
Mask 8: Metal
Mask 4: Gate / Field Oxide
Mask 6: N Plus Contact
Mask 2: N Plus Implant
Mask 3: N drift Implant
Metal
Metal
Oxide
Oxide
Oxide
Gate metal
N cont
Gate Oxide
N cont
P-type Epitaxy
N plus
N plus
6H-SiC substrate
N drift

13. Device Implementation
Design of Lateral MOSFET in Silicon Carbide
Device Implementation
Appearance of surface after ion implant and unsuccessful anneal
Appearance of surface after ion implant and successful anneal

14. EXCEL Testing Results 4.6E15
Design of Lateral MOSFET in Silicon Carbide
EXCEL Testing Results
4.6E15

15. EXCEL Testing Results 0.02 0.017 1800V 0.015 1200V 0.013 600V 0.01
Design of Lateral MOSFET in Silicon Carbide
EXCEL Testing Results
0.02
0.017
1800V
0.015
1200V
0.013
600V
0.01

16. MEDICI Testing Results
Design of Lateral MOSFET in Silicon Carbide
MEDICI Testing Results
Shows that design requirement is obtainable.
>600V
2.8E+17

17. MEDICI Testing Results
Design of Lateral MOSFET in Silicon Carbide
MEDICI Testing Results
~1450V
2.8E+17

18. MEDICI Testing Results
Design of Lateral MOSFET in Silicon Carbide
MEDICI Testing Results
~ V
2.8E+17

19. CONTACT RESISTANCE (1m-cm2)
Design of Lateral MOSFET in Silicon Carbide
Results
9,000
4, 000
COST
($4,000)
66 x 167
500 x 500
PHYSICAL SIZE
(500 x 500µm)
4.6e15 to 1.3e16
5 e15 to 1e16
EPI GROWTH
(5e15 to 1e16cm-3)
2.32 to 3.4
CONTACT RESISTANCE (1m-cm2)
N/A
13, 15, 17
ON-RESISTANCE
(50, 350, 2450m-cm2)
650, 1450, 1900
BLOCKING VOLTAGE (600, 1200, 1800V)
OBTAINED OBJECTIVE?
ACTUAL RESULTS
SIMULATION RESULTS
REQUIREMENTS ? ?
0.6
Yes
Yes
Yes No
More masks were made than planned and smaller critical dimension tolerance was selected.

20. Design of Lateral MOSFET in Silicon Carbide
Future Work
Optimize layouts (gate length, drift length, overlap spacing) based on results from this design
Utilize future advancements in material process technology
Design on a SiCOI (SiC on Insulator)
Continue research in epitaxy growth methods

21. We would like to give thanks to…
Design of Lateral MOSFET in Silicon Carbide
We would like to give thanks to…
* General Electric Corporate Research and Development - Wafer fabrication and Partial funding
* Office of Naval Research - Partial funding
* EMRL - Providing facilities and SiC research
Special thanks to ...
* Will Draper - Cadence contributions
* Igor Sankin - Medici contributions
* Dr. Steve Saddow - Annealing Process

22. Design of Lateral MOSFET in Silicon Carbide
References

23. Design of Lateral MOSFET in Silicon Carbide
References

24. DESIGN OF LATERAL MOSFET IN SILICON CARBIDE
Mississippi State University
Department of Electrical and Computer Engineering