1. Irradiation results of technologies for a custom DC-DC converter F.Faccio, G.Blanchot, S.Michelis, C.Fuentes, B.Allongue, S.Orlandi CERN – PH-ESE

2. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 2 Outline   Technological background   Irradiation results Vertical high-V transistors Lateral high-V transistors (LDMOS)   HBD applied to high-V transistors   Conclusion

3. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 3 Technology for DCDC ASIC   Buck converter topology has been chosen: need a suitable technology for ASIC development (both low-voltage CMOS for control and high- voltage transistors for the power train)

4. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 4 Technological background   Two strategies for high-V transistors to be added to a “standard” mixed-mode low-V CMOS Vertical Lateral (LDMOS)

5. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 5 Technologies in this study   Main properties of the technologies studied in this work TechnologyTech. nodeTransistor typeMax Vds [V]Max Vgs [V] A 0.35  m Vertical N803.3 LDMOS N143.3 LDMOS P803.3 B 0.25  m LDMOS N222.5 LDMOS P162.5 C 0.18  m LDMOS N & P205.5 D 0.18  m LDMOS N & P201.8 LDMOS N & P501.8 LDMOS N & P255 E 0.13  m LDMOS N & P204.5

6. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 6 Irradiation & measurements   Samples from drop-in process monitors Custom test structures designed in 2 cases   Measurement of static characteristics (Id=f(Vgs, Vds)) with automatic system Using dedicated probe cards Typically room T   TID irradiation @ CERN X-ray facility Up to 350Mrd, 20-66 krd/min Bias: WC and “switched” (SB) Temperature: 27 and -30 o C   Displacement damage: “irrad1” facility at the CERN PS beam (24GeV/c protons) Up to 1 ∙10 16 p/cm 2 Floating bias, room T 1 additional measurement at 5MeV proton beam at LNL, Italy

7. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 7 TID results (1)   V th shifts – as well as degradation of other parameters – in line with gate oxide thickness in the different technologies (both vertical and LDMOS) Best option is the use of thin-oxide technologies   Leakage current increase in NMOS very variable No correlation with voltage ratings, gate oxide thickness or technology node Results for WC bias at room T 0.25um and 0.13um are the best options

8. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 8 TID (2)   Bias and Temperature influence the results (leakage current) sensibly Results for 0.25um technology

9. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 9 Displacement damage (1)   Vertical transistors Large increase of on-resistance Defects in the lowly-doped drift region affect carrier mobility dramatically at high fluence

10. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 10 Displacement damage (2)   LDMOS transistors Increase of on-resistance + distortion of output characteristics (Id=f(Vds)) Fluence for onset of degradation very variable with technologyNMOSPMOS Results for 0.25um technology Results for 0.18um technology

11. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 11 Displacement damage (3)   On-resistance increase for all technologies (LDMOS) NMOSPMOS 0.25um (n- and p-LDMOS) and 0.35um (n-LDMOS) are the best options

12. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 12 HBD techniques   Aimed at eliminating the source-drain leakage current at the edge of n-channel transistors   Different designs possible 2 HBD designs experimented Standard Fully enclosed Thin oxide extended Thick oxide (STI)

13. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 13 HBD applied to high-V transistors   Modified layout of n-channel transistors inspired by techniques used in low-V CMOS Vertical transistor LDMOS in 0.35 and 0.25  m technologies   Efficient to reduce the TID-induced leakage current Vertical LDMOS

14. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 14 HBD applied to high-V transistors   …but the layout modification might affect the high-V capability Vertical transistor No impact detected (field is vertical) LDMOS In one technology, Vds capability compromised after proton irradiation (pre-rad OK)! A different design in the 0.25  m technology OK even after proton irradiation - this can be kept as backup design

15. CMS PWG meeting – September 3, 09F.Faccio – CERN/PH/ESE 15 Conclusion   Systematic measurements of TID and displacement damage in high-V transistors in 5 technologies have been made   TID: results comparable to low-V CMOS Leakage current not directly correlated with technology node, gate oxide thickness, V rating   Displacement damage: strong effect on channel resistance at large integrated fluence Very different sensitivity in the 5 technologies   HBD techniques successfully applied They decrease the TID-induced leakage BUT they might have an impact on the high-V capability   Best technology satisfying our requirements (250Mrd, 2 ∙10 15 n/cm 2 ) is the 0.25um Design of prototypes on-going   Backup technology is the 0.35um Very good prototype already exists and has been irradiated successfully The design could be completed with relatively small effort (backup)   We need a more precise requirement on the radiation tolerance!