1. dspBlk Aim: Capture and simulate dspBlk element ISE Project : appliedVHDL.ise provides access to all constituent files This document contains: EE427 submission / demonstration instructions appliedVHDL project overview Block diagram Assignment Instructions Incremental Data Dictionary Functional Partition Process Description FSM Flow chart EE427 Phase 3d Assignment : Contents

2. dspBlk DFD 1.4 Block Diagram

3. dspBlk Assignment instructions ISE Project : appliedVHDL.ise provides access to all constituent files 1.DSPBlk level –Capture the DSPBlk.vhd VHDL model. The lab file contains commented VHDL template files –Check VHDL code syntax, synthesise and view RTL schematic. Confirm correctness. –Note : Simulation of the DSPBlk is not required. This unit will be simulated at the appliedVHDL level Implementation on FPGA is not required

4. dspBlk ldCnt0 : assertion loads counter cnt with value 0 when DSP process activated. Count value increments after completion of each DSP cycle (two RAM reads, subtract and RAM write), on assertion of incCnt Signal cnt provides dspRamAdd(15:0) values as DSP task progresses (max 216 -1 = 64k) DSP task completes when cnt value = dspAddRange dspAddRange(15:0) : setup (by host write to CSR(4:3)) prior of activation of dspBlk. Defines RAM address, allowing programming of 0  64k dspBlk delta frame cycles regRamDatA : asserted by FSM to register the first RAM data value (from RAM quadrant 0), as dDatFromRam. dDatFromRam : stored and subtracted from the RAM quadrant 1) data value to provide the delta task result (which is then written to RAM quadrant 3) intDspDone : asserted when cnt = dspAddRange, indicating completion of DSP task. Signal is used internally and equivalent to output signal dspDone DFD 1.4 Incremental Data Dictionary

5. dspBlk DFD 1.4 Functional Partition

6. dspBlk DFD 1.4 Process Description Activated on assertion of dspActive Reads RAM 32-bit data value from both RAM quadrant 0 and 1 (ram address bus width is 18 bits => 256k addressable 32-bit longwords) –Quadrant 0 base address (binary) = 00_0000_0000_0000_0000 –Quadrant 0 top address = 00_1111_1111_1111_1111 –Quadrant 1 base address = 01_0000_0000_0000_0000 –Quadrant 1 top address = 01_1111_1111_1111_1111 –Quadrant 2 base address = 10_0000_0000_0000_0000 –Quadrant 2 top address = 10_1111_1111_1111_1111 –Quadrant 3 base address = 11_0000_0000_0000_0000 –Quadrant 3 top address = 11_1111_1111_1111_1111 (256k) Performs data processing (delta calculation in this example) : –Quadrant 1 data - Quadrant 0 data (assume data unsigned) –result written to Quadrant 2 Requires prior setup of DSP RAM address range (dspAddRange(15:0) in dspBlk), allowing programming of 0  64k delta frame cycles dspAddRange(15:0) is stored in CSR(4:3) bytes Asserts dspDone on completion of task

7. dspBlk Reads longword from SRAM quadrant 0 dspRamAdd(17:16) = 00 Reads longword from SRAM quadrant 1 dspRamAdd(17:16) = 01 Registers each SRAM data value Performs subtraction on two SRAM data values writes longword to SRAM quadrant 2 dspRamAdd(17:16) = 10 Continue CSR(4:3) times (16-bit). Max = 64k longword DFD 1.4 Process Description

8. dspBlk DFD 1.4 Finite State Machine (FSM) Flow Chart Flowchart Key (Note : all signal indicated on flowchart paths are asserted ‘1’) i/ps : clk, rst dspActive ramDone intDSPDone o/ps (all default to ‘0’) : dspRamWr dspRamRd ldCnt0 incCnt regRamDatA dspRamAdd(17:16)