1. April 15, 2013 Atul Kwatra Principal Engineer Intel Corporation Hardware/Software Co-design using SystemC/TLM – Challenges & Opportunities ISCUG ’13

2. Agenda  HW/SW Co-design Goals & Challenges  “Shifting-Left” product development using Virtual Platforms  SystemC/TLM use cases & challenges  Summary 2

3. HW/SW Co-design Goals, Challenges & Opportunities  Deliver complex HW/SW systems while meeting aggressive and sometimes contradictory targets –Development time –Development cost –Power –Performance –Area –Product cost  Traditional approaches of developing hardware followed by software no longer sufficient –SW involvement required at HW architecture definition stage  Virtual Platforms can help “shift-left” all aspects of product development and deployment (Architecture, Design, Software, Validation) & Marketing 3 Gaps in SystemC TLM standards & Tools need to be rapidly addressed

4. Virtual Platform Goals & Focus areas  Enable “shift-left” for all aspects of product development  Address multiple focus areas –Register accurate functional modeling –Cycle-level performance modeling –High Level Synthesis –Power modeling –Hybrid Virtual platforms (Simulation + FPGA’s/ emulation) –External customer enabling  Opportunity to leverage standards based SystemC TLM modeling infrastructure (ASI/OSCI*) for multiple use cases 4 Motivation: TTM improvement, Development cost reduction, Competitive Perf/Watt/$ *ASI/OSCI – Accellera Systems Initiative/Open SystemC Initiative Integrated / Inter-operable solutions are required for successful product development & deployment!

5. Simulation Engine Platform SoC Virtual Platform Vision CPU(s) (Functional and/or Performance Model) IP Block Model (internal or external) IP Block Model System I/O Model Mem. Ctrl Model System I/O Model Standard I/O Interface Memory Ethernet, USB, … Virtual I/O Existing or HLS generated RTL RTL-Model Adaptor RTL Transactor CPU SW Debugger Enable efficient Architecture definition, Design, Validation, & SW development IP Block Functional Model Power Model Performance Model Mixed-Level VP FPGA/Emulator (Hybrid VP) HW Accelerator IP Accelerator FW Debugger Bus Model Test Cards 5

6. Register accurate functional modeling  Usage Cases (LT Abstraction Level) –Goal 1: Enable early HW/SW Co-Design –Model = Architecture Specification –Enables very early SW feedback for HW architecture –Goal 2: Enable pre-Si SW usages –BIOS/Firmware development, OS bring-up –Device driver & Application development –Pre-Si & Post-Si system validation test readiness  Gaps –Simulation Performance: Multi-threaded simulation capability –Simulation features (Save-Restore/Check-pointing) and standards for register implementation –Need to speed up CCI (Configuration, Control & Inspection) WG deliverables! –Verification: SCV improvements for UVM

7. Cycle-level Performance Modeling  Usage Cases (AT Abstraction Level) –Architecture & Micro-architecture exploration –System level performance projections –Performance Validation: Model vs. RTL correlation –Functional / Performance mode Switching (Mixed-level VP)  Gaps –Standards-base abstraction level switching mechanism –e.g. LT/AT Switching –Multi-abstraction modeling challenges – model source code structuring & management

8. High Level Synthesis  Usages –High Level Models become the Golden reference and accompany/replace the architecture specification document –Opportunity for HLS derived RTL usage for early Power, Area, and Performance estimations/tradeoff’s –Gap: standard mechanism for virtual platform back- annotation to enable system level –HLS derived RTL usage for final implementation –Tools are maturing…and delivering promising results!  Gaps / Challenges: –Easier derivation of HLS input from TLM models –Need to minimize the number of model sources

9. Power Modeling  Usages –Enables power analysis within the simulation framework –Enables System level power projections –Enables power management SW development and enabling  Gap –Standards based mechanism to implement power specific properties in models

10.  Concept –External partner “end-system” TTM reduction is of immense importance for silicon component providers –Virtual Platforms provide an opportunity to help achieve that goal  Usages –Software development “shifts-left” and begins prior to Silicon component and HW system availability –Integration & test pulled to the left in time, where bugs are cheaper, easier, and quicker to fix –Overall reduction in Time To Market  Challenges: –Module level interoperability in presence of custom TLM extensions –Desire to share models with multiple levels of abstraction is hampered by lack of a standard IP protection mechanism External Customer Enabling 10

11. Summary  HW/SW Co-design is a requirement for delivering complex systems  Virtual Platforms supporting industry standards can enable HW/SW co-design and significantly improve TTM for Silicon and System developers  The SystemC TLM industry standard driven by ASI is making steady progress Call to Action: ASI, Tools providers, Silicon and System developers must work jointly to accelerate the progress of standards!