1. CEA DSM Irfu IDeF-X HD Imaging Detector Front-end for X-ray with High Dynamic range Alicja Michalowska, CEA-IRFU 1 Journées VLSI June 2010

2. CEA DSM Irfu Outline 2 Journées VLSI June 2010 Context Design Results Perspectives

3. CEA DSM Irfu Context 3 Journées VLSI June 2010 2009 Simbol-X mission stopped by CNES=> MACSI project Kick-off. MACSI: Modular Assembly of Caliste Spectro Imager Objective: build a new gamma-camera for space applications made of 8 Caliste 256.

4. CEA DSM Irfu MACSI camera step by step 4 Journées VLSI June 2010 MACSI: 8 Caliste 256

5. CEA DSM Irfu Specifications: module Caliste 256 V1 MACSI: readout of 8 Caliste in a 4x2x3cm 3 camera cooled down to -30°C. MACSI with V1: 392 pins, 6.4 Watt !  power reduction and pin-out compression !  New CALISTE  New ASIC: IDeF-X HD Journées VLSI June 2010 5 256 pixel 8 ASICs 800 mW 49 pins

6. CEA DSM Irfu Specifications: ASIC Journées VLSI June 2010 6 IDeF-X HD for Caliste V2IDeF-X for Caliste V1 Self-triggered ASIC for pixelated Cd(Zn)Te detector with low dark current (few pA) 32 channels AMS CMOS 0.35µm <1keV FWHM at 60keV (2pF,20pA)0.9 keV at 60keV (Caliste V1) LTH<4keV (2pF, 20pA, 6 sigma)2keV (Caliste V1) < 30mW96mW Dynamic range > 1MeV250 keV SEL “immune”SEL LET >60MeV/(mg/cm²) Multi-ASIC digital interface Absolute T sensor (-50 °C  +30°C)

7. CEA DSM Irfu IDeF-X HD: Architecture Submitted:december 2009 Come back from fondry: february 2010 Picture of the layout with the different stages, dimensions, ratio between analog and digital part, presentation of the main parts of the layout. Channel, temperature sensor, digital part, buffer…. Journées VLSI June 2010 7 32 channels CSA (23µA, C IN =2.9pF)= +NSNSCSA (23µA, C IN =2.9pF)= +NSNS Gain (50, 100, 150, 200mV/fC)Gain (50, 100, 150, 200mV/fC) PZ cancellationPZ cancellation RC² filter (T PEAK =1 to 13µs)RC² filter (T PEAK =1 to 13µs) Base Line Holder (switchable)Base Line Holder (switchable) Peak detectorPeak detector Discriminator with DAC (6 bits)Discriminator with DAC (6 bits) GLOBAL OR to Trigger output.GLOBAL OR to Trigger output. Energy and T readout via differential output buffer.Energy and T readout via differential output buffer. 3 Readout modes3 Readout modes –Hit channel(s) –All channel –On demand Slow ControlSlow Control –Gain –T PEAK –I CSA (23-100µA) –Threshold (-135el -> 3.6 kel @ 200mV/fC)) –I LEAK –Test mask –AlimON Power on resetPower on reset LVDS input/outputLVDS input/output Hardened digital standard cellHardened digital standard cell TsensorTsensor PNP transistor with variable bias current.PNP transistor with variable bias current. Absolute resolution of 0.5°C (from monte-carlo simulation !)Absolute resolution of 0.5°C (from monte-carlo simulation !)

8. CEA DSM Irfu IDeF-X HD Technology: CMOS AMS 0.35µm Area: 5.8 x 2.5 mm² Number of transistors: 100 000 Package: no Run: December 2009 Delivery: February 2010 Test: start in April Journées VLSI June 2010 8 5800 µm 2500 µm

9. CEA DSM Irfu 9 Journées VLSI June 2010 IDeF-X HD measurement results

10. CEA DSM Irfu Measurements: Power consumption and MultiASIC interface 10 Journées VLSI June 2010 Power consumptionPower consumption total: 25.6mW per channel: 0.8mW Multi ASIC interfaceMulti ASIC interfaceCALISTE: -Pinout reduced down to 16 (49 in V1) -All signals shared between Caliste ASICs Functionality verified: read / write ADDR1 DATA ADDR IN IGNORE DATA ADDR2 ACCEPT DATA IDeF-X 1 IDeF-X 2 CONTOLER

11. CEA DSM Irfu Measurements: Linearity and Dynamic Range 11 Journées VLSI June 2010 Theoretical gain [mV/fC] Measured gain [mV/fC] Dynamic range [fC] Dynamic range [eV] CdTe INL [%] 5051.836.05/ 40.60.99 M / 1.12 M1.19 / 1.77 100102.221.9604 k1.39 150152.513.65377 k1.04 200203.88.6237 k0.82 Results obtained at Filter output on spy channel. T PEAK =10.73µs I LEAK =20pA T AMBIANT

12. CEA DSM Irfu Measurements: ENC vs Peaking Time 12 Journées VLSI June 2010 Different values of leakage current:Different values of leakage current: i LEAK < 1 pA i LEAK = 10 pA i LEAK = 20 pA i LEAK = 100 pA For i LEAK < 1 pA and peaking time 10.7 µsFor i LEAK < 1 pA and peaking time 10.7 µs ENC floor = 33 el For i LEAK ~ 20pA and peaking time 3.39 µsFor i LEAK ~ 20pA and peaking time 3.39 µs ENC = 55 el Gain 200 mV/fC, C IN =0, T AMBIANT, spy channel measurements.

13. CEA DSM Irfu Measurements: Sensitivity to input capacitance 13 Journées VLSI June 2010 For peaking time 10.73 µs and leakage current ~ 20 pA ENC [e] = 66 + 6.4/pF Optimal peaking time: ~6 µs Lowest ENC with 2pF input capacitance ENC = 74 el

14. CEA DSM Irfu Measurements: ENC vs injected charge 14 Journées VLSI June 2010 Without non stationary noise suppression: Reset transistor, Low C F, high dynamic range =>ENC increase with injected charge With non stationary noise suppression: Low pass filter between CSA output and reset transistor =>ENC stable Base line and maximum (50mV/fC, 10.73µs, Q IN =15fC) The noise on the maximum is more than twice the noise on the baseline Base line and maximum (50mV/fC, 10.73µs, Q IN =15fC) The noise on the maximum is the same as the one on the baseline LOW PASS

15. CEA DSM Irfu Measurements: BLH functionality and noise contribution 15 Journées VLSI June 2010 Output baseline vs leakage current :Output baseline vs leakage current : No variation of the Baseline at all with leakage current in range ~0.1 pA.. 4 nA ENC vs peaking time measured with and without Baseline HolderENC vs peaking time measured with and without Baseline Holder Negligible contribution to total channel noise floor

16. CEA DSM Irfu Measurements: Temperature sensor 16 Journées VLSI June 2010 ASIC temperature sensor as function of reference temperature sensor PT100 Measured accuracy of 1.5 ⁰ C in range -45.. 20 ⁰ C

17. CEA DSM Irfu Parameters summary IDeF-X HD 17 Journées VLSI June 2010 SpecificationMeasurement Self-triggered ASIC for pixelated Cd(Zn)Te detector with low dark current (few pA) 32 channels AMS CMOS 0.35µm <1keV FWHM at 60keV (2pF,20pA) 0.9 keV at 60keV (2pF,20pA, t PEAK = 6µs) LTH<4keV (2pF, 20pA, 6 sigma)2keV (2pF,20pA, t PEAK = 6µs) < 30mW25.6mW Dynamic range > 1MeV1.12 MeV Multi-ASIC digital interface16 pins MODULE, verified functionality Absolute T sensor (-50 °C  +30°C)Ok for one chip !

18. CEA DSM Irfu Low T Test Spectroscopy measurements with Cd(Zn)Te detectors ASIC Spatial Qualification (SEU, SEL, dose) Caliste V2 then MACSI fabrication (already initiated) Perspectives 18 Journées VLSI June 2010

19. CEA DSM Irfu 19 Journées VLSI June 2010 Thank you for your attention

20. CEA DSM Irfu Measurements: BLH dynamic performance 20 Journées VLSI June 2010 GREEN: charge injection (voltage step to input serial capacitance) RED: channel response (dynamic behaviour of baseline – stable )

21. CEA DSM Irfu Measurements:BLH dynamic performance 21 Journées VLSI June 2010 GREEN: charge injection (voltage step to input serial capacitance) RED: channel response (dynamic behaviour of baseline – stable) ZOOM to baseline

22. CEA DSM Irfu Measurements: BLH functionality and noise contribution 22 Journées VLSI June 2010 Output baseline vs leakage current :Output baseline vs leakage current : No variation of the Baseline at all with leakage current in range ~0.1 pA.. 4 nA ENC vs peaking time measured with and without Baseline HolderENC vs peaking time measured with and without Baseline Holder Negligible contribution to total channel noise floor

23. CEA DSM Irfu IDeF-X HD: Analog Channel Architecture Submitted:december 2009 Come back from fondry: february 2010 Picture of the layout with the different stages, dimensions, ratio between analog and digital part, presentation of the main parts of the layout. Channel, temperature sensor, digital part, buffer…. Journées VLSI June 2010 23

24. CEA DSM Irfu 24 Analog low noise channel:Analog low noise channel: CSA (2-5pF,ileak=1pA-1nA) + PZCSA (2-5pF,ileak=1pA-1nA) + PZ Filter RC 4 (Sallen&Key)Filter RC 4 (Sallen&Key) A +/- 2 (signal polarity)A +/- 2 (signal polarity) BaselineholderBaselineholder Peak detectorPeak detector DiscriminatorDiscriminator Threshold 6 bits DACThreshold 6 bits DAC Journées VLSI June 2010 Design of the new stages: Non Stationary Noise Suppressor

25. CEA DSM Irfu 25 Analog low noise channelAnalog low noise channel CSA (2-5pF,ileak=1pA-1nA) + PZCSA (2-5pF,ileak=1pA-1nA) + PZ Filter RC 4 (Sallen&Key)Filter RC 4 (Sallen&Key) A +/- 2 (signal polarity)A +/- 2 (signal polarity) BaselineholderBaselineholder Peak detectorPeak detector DiscriminatorDiscriminator Threshold 6 bits DACThreshold 6 bits DAC Journées VLSI June 2010 Design of the new stages: Baseline holder

26. CEA DSM Irfu Measurements: Discriminator 26 Journées VLSI June 2010 S curves measurements at different charge injection level =>Threshold Vs injected charge for each channel => LSB and low threshold extraction by linear fit. Dynamic range>11 keV (44keV) LSB= 215 eV (800 eV) (Simulation gives 200 eV) (en Volt !) at 200 mV/fC (50mV/fC), Ileak=20pA, Tambient at 200 mV/fC (50mV/fC), Ileak=20pA, Tambient