1. Lecture 6: Decision and Control CS 2011 Spring 2016, Dr. Rozier

2. For next time MP0 Your first task is to form into groups of 3-4. E-mail me a list of your 6+2’s and an alphanumeric group username. MP0 will get you acquainted with github and our cluster, as well as some VERY basic ARM. Due next Thursday

3. LADIES AND TIGERS

4. The Lady and the Tiger Doors containing either Ladies or Tigers

5. The Lady and the Tiger Once again, you’ll have to tell Ladies from Tigers A new twist is being added. – Two doors – If a lady is in Room I, then the sign on the door is true. If a tiger is in Room I, then the sign on the door is false. – The opposite is true for Room II.

6. The Lady and the Tiger Q1 Room ?? This room contains a tiger. Both rooms contain tigers Room ??

7. The Lady and the Tiger Q1 Room II Room I

8. The Lady and the Tiger Once again, you’ll have to tell Ladies from Tigers A new twist is being added. – Three doors! – One lady, TWO tigers – At most one of the signs is true

9. The Lady and the Tiger Q2 Room I A tiger is in this room. Room II A lady is in this room. A tiger is in room II. Room III

10. The Lady and the Tiger Q2 Room I Room II Room III

11. The Lady and the Tiger Once again, you’ll have to tell Ladies from Tigers A new twist is being added. – Three doors! – One lady, TWO tigers – The sign on the door of the room with the lady is true. At least one of the other two signs is false!

12. The Lady and the Tiger Q3 Room I A tiger is in room II. Room II A tiger is in this room. A tiger is in room I. Room III

13. The Lady and the Tiger Q3 Room I Room II Room III

14. BASIC INSTRUCTIONS

15. The Memory Hierarchy

16. Load-Store Architecture RISC architectures, like ARM and MIPS utilize a load-store architecture. Memory cannot be part of arithmetic operations. – Only registers can do this Access memory is through loads and stores.

17. Register Memory Architecture Featured on many CISC architectures, like x86 Allows direct access to memory by instructions.

18. Load Store and ARM Register space is pretty cramped!!! LoaD to a Register with LDR SToRe to memory with STR ldr, [ {, }] – Loads a byte from + into str, [ {, }] – Stores a byte from into +

19. Load Store and ARM Example – ldr r0, [r1,r2] Load data from location r1+r2 into r0. – ldr r0, =string Load data from label string into r0. Special cases exist, see ARM manual – Example: ldrb loads a single byte, padded with zeros.

20. Constants or Immediates Operands can contain registers, or immediate values. – An immediate is like a constant – Represent immediates as follows: #20 add r0, r1, #20 – adds 20 to the value of r1 and stores it in r0.

21. Arithmetic Instructions Addition – add, adc, adds, etc Subtraction – sub, sbc, rsb, subs, etc Multiply – mul, mla, etc

22. Move Instruction mov, – mov r0, r1 – copy the contents of r1 into r0. – mov r0, #20 – copy an immediate value of 20 into r0. mvn, – Move negative, negates operand before copying it.

23. Compare Instructions cmp, cmn, Don’t change the operands, update special status register flags. cmp – subtracts operand2 from operand1 and discards the result. cmn – adds operand2 to operand1 and discards the result.

24. CURRENT PROGRAM STATUS REGISTER

25. Status Register Flags Compare instructions and the special “S” versions of instructions (adds, subs, movs) set the status register flags. Can be used with conditional suffixes to make conditionally executed instructions.

26. CPSR The Current Program Status Register – Special register that holds information on the side effects of instructions. – Condition code flags N – Negative result from the ALU Z – Zero result from the ALU C – ALU operation Carried out V – ALU operation oVerflowed

27. CPSR Operand 1 – 32 bits Operand 2 – 32 bits Result – 32 bits

28. CPSR FlagLogical InstArith Inst N = 1No meaningBit 31 of the result has been set. Indicates a negative number for signed operations Z = 1Result bits are all zero Result of the operation was zero C = 1After shift operation a ‘1’ was left in the carry Result was greater than 32 bits V = 1No meaningResult was greater than 31 bits, possible corruption of sign bit

29. CPSR The CPSR bits are set by: Compare/Test instructions: – The only effect of a comparison is to UPDATE THE CONDITIONS FLAGS. CMP : op1 – op2 CMN: op1 + op2 TST: op1 AND op2 TEQ: op1 EOR op2

30. CPSR The CPSR bits are set by: Data processing operations do not normally effect CPSR! – Can be caused to effect them by adding the S bit of the instruction.

31. CPSR The CPSR bits are set by: Data processing operations and CPSR – Add the “S” suffix to set the “S” bit. – ADDS – SUBS – ANDS

32. Conditional Execution The NZCV flags form the basis for conditional execution in the ARM, one of its most powerful features. – Most architectures must use “branch” or “jump” instructions. – The ARM can enable or disable individual instructions based on the CPSR.

33. Conditional Execution

34. Just as the special “S” suffix can be added to set status flags, other suffixes can be added to act on status flags.

35. EQ: Equal Z=1 Using the EQ suffix on an instruction will cause it to only be executed if the zero flag is set. cmp r0, r1 @ Set flags based on r0-r1 adds r0, r1, r2 @ Set flags based on r0 = r1 + r2 movs r0, r1 @ Set flags based on r0 = r1

36. EQ: Equal Z=1 Using the EQ suffix on an instruction will cause it to only be executed if the zero flag is set. Example cmp r0, r1 @ Set flags based on r0-r1 addeq r2, r0, r1 @ Conditional addition

37. NE: Equal Z=0 Using the NE suffix on an instruction will cause it to only be executed if the zero flag is not set.

38. Other conditional suffixes VS – overflow set, V=1 VC – overflow clear, V=0 MI – minus set, N=1 PL – minus clear, N=0 CS – carry set, C=1 CC – carry clear, C=0 AL – always, unconditional NV – never, unconditional

39. Multiple Conditional Suffixes HI – higher (unsigned), C=1 and Z=0 – Unsigned greater than LS – lower (unsigned), C=0 || Z=1 – Unsigned less than GE – greater or equal (signed), N=1 and V=1 OR N=0, V=0 – Signed greater than or equal to LT – less than (signed), N=1 and V=0, OR N=0 and V=1 – Signed less than

40. Multiple Conditional Suffixes GT – greater than (signed), (N=1 and V=1, OR N=0 and V=1) AND Z=0 – Signed greater than LE – less than or equal (signed), (N=1 and V=0, OR N=0 and V=1) OR Z=1 – Signed less than or equal to

41. Conditional Execution EQ – enable this instruction if the results of the last CMP or “S” instruction indicate equality: Example: CMP r0, r1 ADDEQ r0, r0, r1

42. Conditional Execution To understand conditional execution, let’s think in terms of CMP. – CMP r0, r1 What does this mean to the processor?

43. Conditional Execution To understand conditional execution, let’s think in terms of CMP. – CMP r0, r1 r0 - r1, and set NZCV flags – EQ is the conditional execution suffix for r0 == r1. – NE is the conditional execution suffix for r0 != r1. – HI is the unsigned conditional execution suffix for r0 > r1 – LO is the unsigned conditional execution suffix for r0 < r1 In groups, what are the values of NZCV that enable these conditionals?

44. Conditional Execution To understand conditional execution, let’s think in terms of CMP. – CMP r0, r1 r0 - r1, and set NZCV flags – HS is the conditional execution suffix for r0 >= r1. – LS is the conditional execution suffix for r0 <= r1. In groups, what are the values of NZCV that enable these conditionals?

45. Conditional Execution How would you build GT, GE and LT, LE (the signed equivalents)?

46. Conditional Execution CodeSuffixMeaningCodeSuffixMeaning 0000EQZ = 11001LSC = 0 || Z = 1 0001NEZ = 01010GE(N=1 && V=1) || (N=0 && V=0) 0010HS/CSC = 11011LT(N=1 && V=0) || (N=0 && V=1) 0011LO/CCC = 01100GTZ=0 && ((N=1 && V=1) || (N=0 && V=0)) 0100MIN = 11101LEZ=1 || ((N=1 && V=0) || (N=0 && V=1)) 0101PLN = 01110ALAlways 0110VSV = 11111NVReserved/deprec ated 0111VCV = 0 1000HIC = 1 && Z = 0

47. BRANCHING

48. Branching Conditional execution isn’t the only tool in our belt.

49. Branching Branches allow us to transfer control of the program to a new address. – b ( ) – bl ( ) b start bl start

50. Branching Basic branches do not operate on registers. Typically we branch to an indicated LABEL, example: MAIN: b END END: b MAIN

51. Branching Branches are calculated by the assembler relative to the current address. – Allows branching +/- 32 Mbytes Branch stores the target address in the Program Counter Branch and link also stores the next address in the link register.

52. Branch (b) Branch, possibly conditionally, to a new address. beq subroutine @ If Z=1, branch Good practice to use bal instead of b.

53. Branch with link (bl) Branch, possibly conditionally, to a new address. – Before the branch is complete, store the PC in the LR. – Allows easy return from the branch. bleq subroutine @ If Z=1, branch, saving the PC

54. Branch with link (bl) How do we get back once we’ve saved the PC? mov pc, lr Moves the contents of the link register to the program counter.

55. Implementing If Statements C code: if (i == j) f = g+h; else f = g - h; ARM code cmp r0, r1 @ Set flags via r0-r1 and discard beq Else add r2, r3, r4 @ r2 = r3 + r4 bal Exit Else: sub r2, r3, r4 @ r2 = r3 + r4 Exit:

56. Implementing Loop Statements C code: while (i < j) i += 1; ARM code Loop: cmp r0, r1 bge Exit add r0, r0, #1 bal Loop Exit: i < j? i=i+1 i<j Exit i>=j

57. Basic Blocks A basic block is a sequence of instructions with – No embedded branches (except at end) – No branch targets (except at beginning) A compiler identifies basic blocks for optimization An advanced processor can accelerate execution of basic blocks