1. 1 Instructions and Addressing http://www.pds.ewi.tudelft.nl/~iosup/Courses/2012_ti1400_3.ppt Course website: http://www.pds.ewi.tudelft.nl/~iosup/Courses/2012_ti1400_results.htm

2. TU-Delft TI1400/12-PDS 22 Lecture 1 Making functions time A,B Y  A B Y ADD nand gates

3. TU-Delft TI1400/12-PDS 3 Lecture 1 Making functions Circuit Diagram http://xkcd.com/730/

4. TU-Delft TI1400/12-PDS 4 Lecture 2 Programmable device 2,1 3 Programmable Device input stream output stream program READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) READ(X) means read next input value from input stream and store it internally as variable X WRITE(X) means put value in variable X on output stream ADD(X,Y,Z) means assign value of X+Y to Z

5. TU-Delft TI1400/12-PDS 5 Lecture 2 Von Neumann Architecture READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) X: 1 Y: 2 Z: 3 TEMP_A: TEMP_B: RESULT: IR: PC: arithmetic unit Central Processing Unit CONTROL Memory Input Output

6. TU-Delft TI1400/12-PDS 6 Problem: How to Represent and Use Data? 1.Representation 2.Arithmetic 3.Conversion

7. TU-Delft TI1400/12-PDS 7 Lecture 2 Von Neumann Architecture READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) X: 1 Y: 2 Z: 3 TEMP_A: TEMP_B: RESULT: IR: PC: arithmetic unit Central Processing Unit CONTROL Memory Input Output

8. TU-Delft TI1400/12-PDS 8 Problem: How to Represent and Use Data Instructions? 1.Representation 2.Use (Addressing Data)

9. TU-Delft TI1400/12-PDS 99 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing

10. TU-Delft TI1400/12-PDS 10 Computer System READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) X: 1 Y: 2 Z: 3 IR: PC: arithmetic unit Central Processing Unit control unit Main Memory Input Output registers Data and Instructions Instruction RegisterProgram Counter

11. TU-Delft TI1400/12-PDS Intuition: Bits = Rooms, Bytes = Houses, Words = House Blocks, Memory = ? 11

12. TU-Delft TI1400/12-PDS 12 Main Memory Addressing 0 00000000000000000000000 00000000 0 00000000000000000000000 00000000 0 00000000000000000000000 00000000 Bit Byte (8 bits) Word (16-64 bits) Address 0 Address 31 0 81624 123 0

13. TU-Delft TI1400/12-PDS 13 Q1: How many bits required to address? 1.1KB of memory A.By Bit (13) B.By Byte (10) C.By Word of 32 bits (8) 2.1MB of memory A.By Bit (23) B.By Byte (20) C.By Word of 32 bits (18) 3.1GB of memory A.By Bit B.By Byte C.By Word of 32 bits 4.1TB of memory A.By Bit B.By Byte C.By Word of 32 bits Q2: How much memory can be addressed by byte for a 32-bit architecture? Q3: Why use byte memory addressing?

14. TU-Delft TI1400/12-PDS Instruction Set Architecture [1/2] Instructions a computer can perform (instr. type) + Instruction format Common instruction types -Data copy (memory to register, etc.) -Data processing (arithmetic, etc.) -Program control (IF statements, etc.) Common instruction formats -General format (opcode + operands) -Other formats 14

15. TU-Delft TI1400/12-PDS Instruction Set Architecture [2/2] Types of ISAs 1.How are instructions aligned with the memory? 2.Which types of instructions? 3.How many explicit operands to allow per instruction? 4.Where are operands stored in the CPU? (reg/acc/stk) 5.How to access operands? 6.Other questions: Which instructions can access memory? Etc. 15

16. TU-Delft TI1400/12-PDS 16 Instruction and wordlength (1/3) instruction 0 1 2 3 4 5 6 7 8 9 10 word instruction instruction 0 1 2 3 4 5 6 7 8 9 10 word address

17. TU-Delft TI1400/12-PDS 17 Instruction and wordlength (2/3) instruction instruction 0 1 2 3 4 5 6 7 8 9 10 word address instruction instruction

18. TU-Delft TI1400/12-PDS 18 Instruction and wordlength (3/3) 0 1 2 3 4 5 6 7 8 9 10 word address instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr

19. TU-Delft TI1400/12-PDS 19 32 bit word formats opcode specifier operand specifiers 31 30 1 0 byte byte byte byte a two’s complement number 4 ASCII characters 32 bit a machine instruction

20. TU-Delft TI1400/12-PDS 20 Byte ordering (endianness) 0123 4567 89-- ---- ---- 0 2 1 Word Index Big endian e.g., Motorola PowerPC 68k Little endian e.g., Intel Jonathan Swift’s Gulliver’s Travells 3210 7654 --98 ---- 0 2 1 ----

21. TU-Delft TI1400/12-PDS 21 Q1 (the NUXI problem) What problems can occur in porting data between machines with big-endian and little-endian storage? (Hint: networked machines) Q2 Why use the little endian byte ordering? Q3 Why use the big endian byte ordering? (Hint: value 4 as single- and multi-byte)

22. TU-Delft TI1400/12-PDS 22 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing 2.1. Data Copy Operations 2.2. Arithmetic And Logic Ops. 2.3. Program flow control Ops. 2.4. I/O operations

23. TU-Delft TI1400/12-PDS 23 Types of Instructions Common modern computers have 4 types of instructions -Data Copy operations between memory and registers between memory locations between registers -Arithmetic and Logic operations -Program flow control operations -I/O operations

24. TU-Delft TI1400/12-PDS 24 Symbolic notation Copy instructions [R 1 ]  M(LOC) Arithmetic operations M(C )  M(A ) + M(B) LOC, A, and B are memory addresses M(address) means contents of memory location at address. [R] means contents of register R.

25. TU-Delft TI1400/12-PDS 25 Operand specification formats Three-address instructions format: INSTR source#1,source#2,destination example: Add A,B,C means: M(C )  M(B) + M(A) Problem: 3-address instructions means long instruction words. -If k bits are needed for memory addressing, then 3k bits are needed for addressing operands. (k=32 for 32-bit platforms.)

26. TU-Delft TI1400/12-PDS 26 Operand specification formats Two address instructions format: INSTR source, destination example: Add A,B means: M(B)  M(B) + M(A) Problem: 2-address instructions mean somewhat long word or multiple FETCHes per instruction. -If k bits are needed for memory addressing, then 2k bits for addressing operands. (k=32 for 32-bit platforms.)

27. TU-Delft TI1400/12-PDS 27 Two address instruction Additional Problem: Operand Override Add A,B Two operand instructions destroy contents of the B location Need other instruction to avoid that: Move B,C We then have Move B,C Add A,C meaning: M(C)  M(B) ; M(C)  M(C) + M(A) ;

28. TU-Delft TI1400/12-PDS 28 One address instructions One address -have implicit source (often called Accumulator) Load A Add B Store C meaning [Accu ]  M(A) ; [Accu ]  [Accu ] + M(B) ; M(C)  [Accu ]

29. TU-Delft TI1400/12-PDS 29 Instruction Formats (Summary) opcode specifier operand specifiers general format one operand addressing opcode operand operand two operand addressing opcode operand

30. TU-Delft TI1400/12-PDS 30 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing

31. TU-Delft TI1400/12-PDS 31 Registers Many computers have a number of General- Purpose registers inside the CPU Access to registers is faster than to memory locations Used to store temporary data during processing Registers require less bits of address than main memory

32. TU-Delft TI1400/12-PDS 32 Register addressing Let Ri denote register General operation ADD A,B,C can be broken down to Move A,R0 Add B,R0 Store R0,C meaning [R0]  M(A) ; [R0]  [R0] + M(B) ; M(C)  [R0]

33. TU-Delft TI1400/12-PDS 33 Accumulator architecture Accumulator PC CPU Main Memory

34. 34 Question How many instructions can be defined when the opcode field is 5 bit ?

35. TU-Delft TI1400/12-PDS 35 Example instruction accu 4 bits 12 bits opcode operand m 15 0 sign bit

36. TU-Delft TI1400/12-PDS 36 Instruction set

37. TU-Delft TI1400/12-PDS 37 Multiple register architecture R0 CPU Main Memory R1 R2 R3

38. TU-Delft TI1400/12-PDS 38 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing

39. TU-Delft TI1400/12-PDS 39 Straight-line sequencing …... ……. Move A,R0 Add B,R0 Move R0,C i i+4 i+8 A B C address Program for M(C)=M(B)+M(A)

40. TU-Delft TI1400/12-PDS 40 Straight-line sequencing Add Nn,R0 Move R0,S Move N1,R0 Add N2,R0 Add N3,R0 i i+4 i+8 i+4n-4 i+4n address Program for addition of n numbers

41. TU-Delft TI1400/12-PDS 41 Branching...... n Clear R0 Move N,R1 Decr R1 Branch>0 L Move R0,S L S N N1 Nn Program for addition of n numbers Determine address of “next” number and add it to R0 program loop

42. TU-Delft TI1400/12-PDS 42 Common branch conditions N (negative) set to 1 of result is negative Z (zero) set to 1 of result is zero V (overflow) set to 1 of result overflows C (carry) set to 1 of carry-out results

43. 43 Question Why is the carry condition important?

44. TU-Delft TI1400/12-PDS 44 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing 5.1. Addressing Modes 5.2. Immediate Addressing 5.3. Direct Addressing 5.4. Indirect Addressing 5.5. Index Addressing

45. TU-Delft TI1400/12-PDS 45 Addressing modes Addressing modes determine how the address of operands is determined Typical 4 addressing modes -immediate addressing -direct addressing -indirect addressing -index addressing

46. TU-Delft TI1400/12-PDS 46 Immediate addressing (1) opcode specifier operand instruction ADD # -1 JNZ 10 10 example: simple counting loop

47. TU-Delft TI1400/12-PDS 47 Immediate addressing (2) Advantages: -no additional calculations needed to obtain operand -fast Disadvantages: -Operand value must be known -Operand value cannot be changed -Limited no of bits available Notation: MOVE #200,R0 Meaning: [ R0 ]  200

48. TU-Delft TI1400/12-PDS 48 Direct addressing(1) opcode specifier mem or reg address instruction memory or registers ADD 13 JNZ 10 # -1 10 13

49. TU-Delft TI1400/12-PDS 49 Direct addressing(2) Advantages: -Operand separate from instruction -Can be changed -Full word length available Disadvantages: -More memory accesses -More storage occupation Notation: ADD R1,R2 Meaning: [ R2 ]  [ R2 ] +[ R1 ] Also called “Absolute addressing” (Ham.)

50. TU-Delft TI1400/12-PDS 50 Indirect addressing (1) ADD (12) JNZ 10 13 # -1 10 13 opcode specifier mem or reg address instruction op. address operand memory or registers

51. TU-Delft TI1400/12-PDS 51 Indirect addressing (2) Advantages: -Actual address of operand is not in instruction -Can be changed Disadvantages: -Even more memory or register references -More memory occupation Notation: ADD (R1),R2 Meaning: [ R2 ]  [ R2 ] + M( [ R1 ])

52. TU-Delft TI1400/12-PDS 52 Example indirect addressing program loop L N N1 Clear R0 Move N,R1 Move #N1,R2 Add (R2),R0 Add #4,R2 Decr R1 Branch>0 L Move R0,S n S

53. TU-Delft TI1400/12-PDS 53 Index addressing (1) opcode Reg index instruction operand memory or registers operand + registers

54. TU-Delft TI1400/12-PDS 54 Index addressing (2) Advantages: -Allows specification of fixed offset to operand address Disadvantages: -Extra addition to operand address Notation: ADD X(R1),R3 (X=number) Meaning: [ R3 ]  [ R3 ] + M( [ R1 ] + X )

55. TU-Delft TI1400/12-PDS 55 Example index addressing NENE Program with index addressing program loop sex age salary n Empoyee ID sex age salary Empoyee ID L Move #E,R0 Move N,R1 Clear R2 Add 8(R0),R2 Add #16,R0 Decrement R1 Branch>0 L Div R1,R2 Move R2,Sum Move N,R1

56. TU-Delft TI1400/12-PDS 56 Additional modes Some computers have auto-increment (decrement instructions) Example: (R0)+ Meaning.. M(R0 )..; [ R0 ]  [ R0 ]+1 Example: - (R0) Meaning [ R0 ]  [ R0 ]-1;.. M(R0 )..