1. Implementing RISC Multi Core Processor Using HLS Language - BLUESPEC Liam Wigdor Instructor Mony Orbach Shirel Josef Semesterial Winter 2013

2. AGENDA Motivation Project Goals Solution Algorithm Project Diagram Development Evnironment Project Gantt

3. Motivation The future of single core is gloomy Multi cores can be used for parallel computing Multi cores may be used as specific accelerators as well as general purpose core. Multi cores may be used to overcome the Dark Silicon problem as different cores can have different properties.

4. Project Goals Main Goal: Implementing RISC multi core processor using BlueSpec Derived Goals: –Learning the BlueSpec principles, syntax and working environment. –Understanding and using RISC processor to implement multi core processor. –Validate design by using simple bench mark programs and evaluating performance to single core.

5. Multi Core architectures GPU initially used the “multi core” concept Memory management performed by memory controller that allocates memory chunks to the “cores” (execution units)

6. Solution Algorithm: In order to improve single core performance we will implement dual core processor with scalability. Steps: First, we will implement processor with 2 cores sharing data memory. Second, we will implement 2 cores with private caches sharing data memory. However, we will use:

7. Design Block Diagram Core 1Core 2 Shared memory Core 1Core 2 Shared memory Cache 1Cache 2 Shared memory and each core has private cache Shared memory without cache

8. Development Evnironment SCE-MI – Provides communications protocols between hardware and software. Xilinx Tools

9. Why BlueSpec? Atomic rules and interface – allow higher level abstraction Synthesizable Verilog RTL 100% architectural transparency Easy to understand code

10. What is SCE-MI? Multiple communication channel that Allow software models to connect to structural models Provides interface between the software and the hardware

11. Xilinx Tools Xilinx ML505 Evaluation Platform Synthesis – from compiling verilog to gate level implementation

12. Project Gantt 2013-2014 29/1222/1215/128/121/1217/1110/113/11 27/10 24/11 Learning BlueSpec Architecture Design Learning single core implementation(without cache) BlueSpec oriented multi- core design (no cache) CDR prep Cache implement if possbile