1. g-2 readout electronics and DAQ Osamu SASAKI (KEK) 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)1

2. Time sequence of the operation The muon beam spill comes every 40 ms (25 Hz). The duration of the measurement is 33  sec. The very high instantaneous event rate requires fine granularity and timing resolution (fine timing slice) for the detectors and front-end electronics in order to reduce the probability of the signal pile-up. Binary readout : ASD + 5 ns sampling (5 ns resolution TDC) + Buffer Memory + Readout The long interval (40 ms) between the measurement and the subsequent spill enables to send all the data after their proper processing to a backend DAQ system. 40 ms 2 ns 33  s 39 ms Beam Injection Measurement Data Processing and Transmission 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)2

3. BufferTx Rx Buffer ASD Test CTRL/Mon. Tx Rx Buffe r TxTx Rx Buffe r TCP/IP CTRL Mon. Tx Rx Buffer Tx RxBuffer TCP/IP CTRL Mon. Frontend Board (on detector) Beam Injection Si Strip Readout Board (VME) Gigabit Ethernet Switch Timing CTRL / Mon. (VME) GPS CLK Generator CTRL/Mon. PC Farm CLK, START BufferTx Rx Buffer ASD Test CTRL/Mon. BufferTx Rx Buffer ASD Test CTRL/Mon. Buffer Tx Rx Buffer ASD Test CTRL/Mon. CLK START CLK START CLK (100MHz) 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)3

4. Block diagram of the front-end board DAQ mode – Tx : Data transmission – Rx : Receive “Real time signals” ; CLK, Start/Stop, Test Pulse, Reset Control mode – Tx / Rx : System configuration and monitoring One of operation modes is alternatively selected. Hit signal sampling every 5 ns Spill Buffer Processor Zero-suppress Spill ID Tx Rx Controller Real Time DAQ Signals System configuration monitoring DAC CLK Start/Stop CLK, Start/Stop, Test Pulse DAQ/Control Configure / monitor ASD Vth Serializer De-serializer Vth 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)4 Front-end ASIC

5. Support from Electronics System Group (E-SYS:KEK) Manobu Tanaka, Tomohisa Uchida and Masahiro Ikeno – Frontend ASIC development and boards/module design. – Valuable advices for system design and mass-production Frontend ASIC – UMCJ (United Microelectronics Cooperation Japan) – UMC 0.25  m CMOS process – First Prototypes are separate chips (4mm x 4mm) with analog and digital parts – Prototype chips will be available in summer 2012. ASD – Preamp + Shaper + Comparator + DAC for Vth Prototype 1 : preamp + shaper + peak-hold + mux – Some circuit configurations will be designed Cascode and folded cascode 5ns sampling (TDC)/Readout – Hit signal sampling every 5 ns – 8k words depth -> 41  s @ 200MHz 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)5

6. Front-end ASIC Sensor Double Sided Silicon Strip Detector (DSSD), 320  m thick AC-coupling, most probable charge 25k e-h pairs (4 fC), C d ~ 30 pF FunctionAmplifier-Sharper-Discriminator (ASD) + TDC + data formatting / readout # of channels128 channels Gain of amp.> 50 mV/MIP, both negative and positive charge inputs Peaking time fast pulse shaping (  < 50 nsec ) Threshold voltageIndividual or offset compensation circuits TDCLeading edge of hit signal, dead-time-less data recording TDC resolution5 nsec Time walk<3nsec Dynamic range 33  sec ReadoutSerial output 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)6

7. ASIC block diagram 5ns stamp DiscriDiscri PreampShaperPreampShaper CompressorSerializerCompressorSerializer DACDAC ControllerController Test pulse,Monitor,Vth,DiscriENB........ FPGAFPGA Analog TEG Analog TEG Digital TEG Digital TEG 7

8. Analog TEG(test element group) 4mmx4mm test pulse in VthVth Shut down Polarity selection ComparatorEnableComparatorEnable Reference voltage DAC control 4bit analog monitor enable enable InputInput MonitoroutputMonitoroutput DigitaloutputDigitaloutput RfRf Rf/5Rf/5 CfCf 5Cf5Cf R/5R/5 RR CfCf 25/05/20128

9. 71mV/MIP Transient response -0.5MIP~-5MIP (0.5MIP step ） Shaper out Preamp out 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)9

10. Shaper out Preamp out Discri. out input -1MIP 5 times(100ns period) 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)10

11. Analog TEG parameterspecsimulation Gain>50mV/MIP~70mV/MIP pulse width<100nsec peaking time CR(RC) 2 ~35n sec Dynamic range ±5MIP ＞ ±5MIP Noise<3000e<2500e DAC4bit10mV/bit # of ch12832 Time walk<<5nsec<5nsec PWD ー ~1mW/ch 60um pitch layout 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)11

12. Digital TEG(test element group) 4mmx4mm Comparator out From analog part Comparator out From analog part MemorywriteControllerMemorywriteController Two phase clk generator Memory 4k words Memory Memory Memory Slow Control I/F Zero data suppressor SerializerSerializer Write start (T0 timing) Write start (T0 timing) MemoryreadControllerMemoryreadController 200MHz200MHz 100MHz100MHz 5nsecx8k 〜 41usec Readout start 4-line serial(SiTCP) 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)12

13. parameterspec System clock 100MHz two phase Sampling clock 200MHz Event buffer 41μsec Serial I/F to FPGA 100 MHz Slow control compatible with the SiTCP # of ch 16 Others circuits for debugging area4mmx4mm Digital TEG Verilog-HDL and Standard-cell(ARM Ltd.) 25/05/2012 2nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE) 13

14. Schedule for ASIC development Project start 2011.08 Design(incl. Layout) completed 2012.2 Evaluation until 2012 summer Next tape out (128ch Prototype) in 2012 JFY 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)14

15. Silicon sensors and frontend board 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)15

16. Mechanical Layout 2nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE) 25/05/201216

17. HV and LV distribution LVPS Floating (on +HV) HVPS DC/DC Si Sensor GND-HV +HV GND-Si Frontend GND-LV +LV +HV-Si GND-FE Signal LVPS FrontendDC/DC +LV GND-LV P N N P Signal GND ON/OFF Current monitor AC coupling Vmax < 20V AC coupling Vmax < 20V 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)17

18. HV/LV supply scheme Individual HV/LV Power Supplies to each Si sensor and each frontend board are not a tolerable solution. – Not only financial but also physical (# of the connections) – Common HV supply with capability of individual current monitoring and ON/OFF – Direct LV feed to frontend electronics is not realistic. ~ 1000A @ 2.5V in total (2mA/ch x 500k = 1kA) Voltage drop in cables – DC/DC converters are one of solutions 36V converted to 2.5V near the detector. Operation in magnetic field (3T)? Pollution to magnetic field ? DSSD – One side is +HV or –HV, and another side is GND signals from both sides. LVPS for signals from HV biased side should be floating and on HV. – The max. rating of the AC coupling is less than 20 V. “Individual ON/OFF of HV” and “common floating LVPS”  any solution ? SSSD – One side is +HV or –HV, and another side is GND – Signals from a GND side. – Common GND for HV and LV. 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)18

19. Vacuum and cooling All the frontend electronics and sensors are in the vacuumed chamber. – Selection of electronics parts, which can be used in vacuum. – No pollution to environment (magnetic field and no electric field) Cooling using some coolant and heat conducting materials. – 5 mW /ch x 400k ch = 2 kW Size of the chamber and total power dissipation are compatible with an oven in a kitchen. Solid R&D works 25/05/20122nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE)19

20. Backup 25/05/2012 2nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE) 20

21. Noise spectrum @ Comparator input 1/f noise Thermal noise Cdet=30pFCdet=30pF 25/05/2012 2nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE) 21

22. ASD-FCGB IRF(uA)IRF4P(uA)noise/gainENC 301010/71.82600 201010/75.72400 10 10/76.92400 20 11/87.52300 352012/89.02500 502012/89.52500 Qinjection -Qinjection 25/05/2012 2nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE) 22

23. time walk v.s. Vth noise=13mV signal=86.3mV 25/05/2012 2nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE) 23

24. Analog TEG parameterspecsimulation Gain>50mV/MIP~70mV/MIP pulse width<100nsec peaking time CR(RC) 2 ~35n sec Dynamic range ±5MIP ＞ ±5MIP Noise<3000e<2500e DAC4bit10mV/bit # of ch12832 Time walk<<5nsec<5nsec PWD ー ~1mW/ch 60um pitch layout 25/05/2012 2nd Workshop on Muon g-2 and EDM in the LHC Era (LPNHE) 24

25. Rx Tx INPUT FIFO DAQ/CTRL Rx Tx INPUT FIFO DAQ/CTRL INPUT FIFO SPILL ID COUNTER STARTSpill CNT Reset TCP/IP OUTPUT FIFO Frontend Control & Monitor VME Protocol START, Test Pulse Trigger, Spill CNT Reset, RESET EXT / INT Spill Event Builder 100 MHz Clock VME CH0 CH7 Run info reg. External Inputs FPGA + CPLD PC from/to FE Boards Destination

26. Beam Injection Test Pulse Trigger Spill CNT Reset RESET 100 MHz CLK /Q D D Q VME Protocol START Test Pulse Trigger Spill CNT Reset RESET Rx Tx INPUT FIFO SPILL ID COUNTER TCP/IP OUTPUT FIFO External Inputs Fanout & to Readout Boards TDC Start Stop START Beam Injection 100 MHz CLK CLK Spill CNT Reset Real Time Signal Monitor & Control PC Real Time Signals from SW INPUT FIFO FE Board Emulation Real Time Signals FPGA + CPLD from Readout Board

27. HV / LV distributor box sensor Current monitor DC/DC frontend ON/OFF 36V HV 2.5V FPGA Control/monitor

28. Frequency Standard