1. Computer Architecture
Chapter 8: Input/Output

2. Input/Output Problems
Wide variety of peripherals
Delivering different amounts of data
At different speeds
In different formats
All slower than CPU and RAM
Need I/O modules

3. Concept of I/O module
Every computer supports a variety of peripheral devices. Two modules required for using peripheral devices:
a) Hardware module called I/O controller
b) Software module called I/O driver

4. Input/Output Module Interface to CPU and Memory
Interface to one or more peripherals
Generic Model of I/O Module

5. Categories of External Devices
Human readable: suitable for communicating with the computer user
Screen, printer, keyboard, mouse
Machine readable: suitable for communicating with equipment
Magnetic disks, tape systems, sensor, actuators
Communication: Suitable for communicating with remote devices
Modem
Network Interface Card (NIC)

6. External Device Block Diagram
The interface to the I/O module is in the form of control, data and status signals Device communication.

7. Control, data and status signals.
Control signals – determine the function that the device will perform. (e.g send data to I/O module, accept data from I/O module, report status)
Data signals – in the form of a set of bits to be sent or to receive from I/O module.
Status signals – indicate the state of the device. (e.g READY/NOT-READY for data transfer)

8. I/O Module Function These are the major functions of I/O module
Control & Timing – coordinate the flow of traffic internal resources and external devices.
CPU Communication.
Device Communication.
Data Buffering
Error Detection

9. I/O Module Block Diagram
Connects to the computer

10. I/O Module Block Diagram - explanation
The modules connects to the rest of the computer through a set of signal lines (system bus lines).
Data transferred to and from the module are buffered in one or more data registers.
Status registers – provide current status information or function as control register, to accept detailed control information from the processor.
The I/O logic- interacts with the processor via a set of control lines.
The processor uses the control lines to issue command to I/O module.
Some of the control lines – used by the I/O module for arbitration and status signals.
The module must be able to recognize and generate address associated with the device it controls.

11. I/O Steps : Transfers data from external device to the processor/CPU
CPU checks I/O module device status
I/O module returns status
If ready, CPU requests data transfer
I/O module gets data from external device
I/O module transfers data to CPU

12. I/O Module Decisions Hide or reveal device properties to CPU
Support multiple or single device
Control device functions or leave for CPU
i/o channel or i/o processor
i/o controller or device controller

13. Input Output Techniques
Three techniques are possible for I/O operations:-
Programmed I/O
Data are exchanged between CPU and I/O module. CPU executes a program that gives the direct control of the I/O operation including sensing device status, sending read or write command and transferring the data. CPU issues command to the I/O module, it must wait until I/O operation complete wasteful of processor time.
Interrupt driven I/O
CPU issues I/O command , continues to execute other instructions and interrupted by the I/O module when the module completed it I/O operation.
Direct Memory Access (DMA)
I/O module and main memory exchange data directly without CPU involvement.

14. Three Techniques for Input of a Block of Data

15. Programmed I/O - detail
CPU requests I/O operation
I/O module performs operation
I/O module sets status bits
CPU checks status bits periodically
I/O module does not inform CPU directly
I/O module does not interrupt CPU
CPU may wait or come back later

16. I/O Commands* CPU issues address CPU issues command
Identifies module (& device if >1 per module)
CPU issues command
Control - telling module what to do
e.g. spin up disk
Test - check status
e.g. power? Error?
Read/Write
Module transfers data via buffer from/to device
*To execute an i/o related instruction

17. Addressing I/O Devices
When the processor issues an I/O command, the command contains the address of the desired device.
Each I/O module must interpret the address lines to determine if the command is for itself.
Under programmed I/O data transfer is very like memory access
Each device given unique identifier or address
CPU commands contain identifier (address)

18. I/O Mapping (2 programmed I/O techniques)
Processor, main memory and I/O share a common bus. 2 modes of addressing possible.
Memory mapped I/O
Devices and memory share an address space
Uses single address space for memory locations and I/O devices.
CPU treats the status and data registers of I/O modules as memory locations and uses the same machine instructions.
No special commands for I/O
Isolated I/O
Separate address spaces
Need I/O or memory select lines
Special commands for I/O
Limited set

19. Memory Mapped and Isolated I/O
(refer stalling p/g 203)

20. Interrupt Driven I/O Overcomes CPU waiting
No repeated CPU checking of device
I/O module interrupts when ready

21. Interrupt Driven I/O Basic Operation
CPU issues read command
I/O module gets data from peripheral whilst CPU does other work
I/O module interrupts CPU
CPU requests data
I/O module transfers data

22. Simple Interrupt Processing
PSW= Programme status word minimum information need by processor to resume the interrupted program.

23. CPU Viewpoint Issue read command Does other work
Check for interrupt at end of each instruction cycle
If interrupted:-
Save context (registers)
Process interrupt
Fetch data & store

24. Changes in Memory and Registers for an Interrupt

25. Explanation
User program is interrupted after instruction at location N.
The contents of all registers + the address of next instruction (N+1) are pushed onto stack.
The stack pointer is updated to point to the new top of stack, and the PC is updated to point to the beginning of the interrupt service routine.
The interrupt handler process the interrupt.
When complete, the saved register values are retrieved from the stack and restored to the registers.
Finally, restore the PSW and PC values from the stack.
Execute the interrupted program (N+1).

26. Multiple interrupt 4 Techniques
How does the processor determine which devices issued the interrupt?
How does the processor decide which one to process?
…multiple interrupt lines, software poll, daisy chain, bus arbitration…..
4 Techniques

27. Identifying Interrupting Module (1)
Multiple interrupt lines
Between processor and I/O modules.
Limits number of devices
Impractical
Software poll
CPU asks each module in turn or check modules’ registers
Slow-time consuming

28. Identifying Interrupting Module (2)
Daisy Chain or Hardware poll
More efficient
All I/O modules share a common interrupt request line
Processor senses interrupt- send Interrupt acknowledge signal
Module responsible places a word on data lines . The word referred to as vector – address of I/O module or some unique identifier.
CPU uses vector to identify handler routine-avoids the need to execute a general ISR  vectored interrupt.

29. Identifying Interrupting Module (3)
Bus Master/bus arbitration
Also makes use of the vectored interrupts.
I/O module first gain control of the bus before it request for interrupt  thus only one module raise the line at a time
Processor detects the interrupt and acknowledge by sending interrupt acknowledge signal.
The requesting module places its vector on the data lines.

30. Example - PC Bus Intel 80386 has one interrupt line
Single INTR (int. req.) and INTA (int. ack) line
To support multiple interrupt, based systems use one 8259A external interrupt arbiter.
8259A has 8 interrupt lines

31. Concept of Multiple Interrupts
Each interrupt line has a priority
Higher priority lines can interrupt lower priority lines
If bus mastering, only current master can interrupt

32. Sequence of Events 8259A accepts interrupts 8259A determines priority
8259A signals (raises INTR line)
CPU Acknowledges
8259A puts correct vector on data bus
CPU processes interrupt

33. 82C59A Interrupt Controller

34. Intel 82C55A Programmable Peripheral Interface
Mode 0 – port A,B,C as I/O port (input or output)
Otherwise, A,B I/O but C as control lines for A and B
Programmable by the by means of the control reg.
External interface
( 24 lines-ABC)
Internal interface
2 addr. lines
Example of I/O module used for programmed I/O and interrupt driven I/O.

35. Example of application: Keyboard/Display Interfaces to 82C55A
Used to control keyboard / display terminal.
Keyboard provides 8 bits input
Display linked to 8 bits data port

36. Direct Memory Access
Interrupt driven and programmed I/O require active CPU intervention.
2 drawbacks of previous methods (programmed and Interrupt driven I/O)
Transfer rate is limited by the speed of CPU
CPU is tied up
DMA used for large volumes of data transfer

37. DMA Function
Additional Module (hardware) on bus which forms a mimicking role of CPU
DMA controller takes over from CPU for I/O

38. Typical DMA Module Diagram
Data count register
Stores the number of words to be read or written.
Data Register.
-the address of the I/O device involved
Address register
-the starting location in memory to read from/ to write to.
Read/write requested by CPU

39. DMA Operation CPU tells DMA controller:-
Read/Write
Device address
Starting address of memory block for data
Amount of data to be transferred
CPU carries on with other work
DMA controller deals with transfer
DMA controller sends interrupt when finished
CPU delegated the I/O operation to the DMA module, CPU only involved at the beginning and at the end of the data transfer.

40. DMA Transfer Cycle Stealing
DMA controller takes over bus for a cycle
Transfer of one word of data
Not an interrupt
CPU does not switch context
CPU suspended just before it accesses bus
i.e. before an operand or data fetch or a data write
Slows down CPU but not as much as CPU doing transfer

41. DMA and Interrupt Breakpoints During an Instruction Cycle
Processor pauses only for one bus cycle.
Multiple-word I/O transfer, DMA is far more efficient than interrupt driven or programmed I/O

42. DMA mechanism DMA mechanism can be configured in a variety of ways.
Single bus-detached DMA
Single bus integrated DMA-I/O
I/O bus.

43. DMA Configurations Single Bus, Detached DMA controller
Each transfer uses bus twice
I/O to DMA then DMA to memory
CPU is suspended twice

44. DMA Configurations Single Bus, Integrated DMA controller
Controller may support >1 device
Each transfer uses bus once
DMA to memory
CPU is suspended once

45. DMA Configurations Separate I/O Bus
Bus supports all DMA enabled devices
Each transfer uses bus once
DMA to memory
CPU is suspended once

46. Intel 8237A DMA Controller Interfaces to 80x86 family and DRAM
When DMA module needs buses it sends HOLD signal to processor
CPU responds HLDA (hold acknowledge)
DMA module can use buses
E.g. transfer data from memory to disk
Device requests service of DMA by pulling DREQ (DMA request) high
DMA puts high on HRQ (hold request),
CPU finishes present bus cycle (not necessarily present instruction) and puts high on HDLA (hold acknowledge). HOLD remains active for duration of DMA
DMA activates DACK (DMA acknowledge), telling device to start transfer
DMA starts transfer by putting address of first byte on address bus and activating MEMR; it then activates IOW to write to peripheral. DMA decrements counter and increments address pointer. Repeat until count reaches zero
DMA deactivates HRQ, giving bus back to CPU

47. 8237 DMA Usage of Systems Bus

48. Fly-By While DMA using buses processor idle
Processor using bus, DMA idle
Known as fly-by DMA controller
Data does not pass through and is not stored in DMA chip
DMA only between I/O port and memory
Not between two I/O ports or two memory locations
Can do memory to memory via register
8237 contains four DMA channels
Programmed independently
Any one active
Numbered 0, 1, 2, and 3

49. I/O Channels I/O devices getting more sophisticated
e.g. 3D graphics cards
CPU instructs I/O controller to do transfer
I/O controller does entire transfer
Improves speed
Takes load off CPU
Dedicated processor is faster

50. I/O Channel Architecture

51. Interfacing Connecting devices together Bit of wire?
Dedicated processor/memory/buses?
E.g. FireWire, InfiniBand

52. IEEE 1394 FireWire High performance serial bus Fast Low cost
Easy to implement
Also being used in digital cameras, VCRs and TV

53. FireWire Configuration
Daisy chain
Up to 63 devices on single port
Really 64 of which one is the interface itself
Up to 1022 buses can be connected with bridges
Automatic configuration
No bus terminators
May be tree structure

54. Simple FireWire Configuration

55. FireWire 3 Layer Stack Physical Link Transaction
Transmission medium, electrical and signaling characteristics
Link
Transmission of data in packets
Transaction
Request-response protocol

56. FireWire Protocol Stack

57. FireWire - Physical Layer
Data rates from 25 to 400Mbps
Two forms of arbitration
Based on tree structure
Root acts as arbiter
First come first served
Natural priority controls simultaneous requests
i.e. who is nearest to root
Fair arbitration
Urgent arbitration

58. FireWire - Link Layer Two transmission types Asynchronous Isochronous
Variable amount of data and several bytes of transaction data transferred as a packet
To explicit address
Acknowledgement returned
Isochronous
Variable amount of data in sequence of fixed size packets at regular intervals
Simplified addressing
No acknowledgement

59. FireWire Subactions

60. InfiniBand I/O specification aimed at high end servers
Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel)
Version 1 released early 2001
Architecture and spec. for data flow between processor and intelligent I/O devices
Intended to replace PCI in servers
Increased capacity, expandability, flexibility

61. InfiniBand Architecture
Remote storage, networking and connection between servers
Attach servers, remote storage, network devices to central fabric of switches and links
Greater server density
Scalable data centre
Independent nodes added as required
I/O distance from server up to
17m using copper
300m multimode fibre optic
10km single mode fibre
Up to 30Gbps
Scsi-is a parallel bus.

62. InfiniBand Switch Fabric

63. InfiniBand Operation
16 logical channels (virtual lanes) per physical link
One lane for management, rest for data
Data in stream of packets
Virtual lane dedicated temporarily to end to end transfer
Switch maps traffic from incoming to outgoing lane

64. InfiniBand Protocol Stack