1. Title 1 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC The Industry’s Fastest NOR Flash Families for the Highest-Performance Embedded Systems New Product Introduction: 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families KL-S/KS-S = Cypress’s 3.0-V/1.8-V, 65-nm NOR Flash Memory with MirrorBit ® Technology

2. 2 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) NOR Flash Memory Terms Nonvolatile Memory (NVM) A memory that retains data even when it is not powered Program Memory A low-latency and high-bandwidth NVM that enables fast execution of CPU instructions Flash Memory An NVM that alters the voltage at which a transistor conducts current by adding or removing electrons to set predefined “1” and “0” states for a memory cell NOR Flash Memory A Flash Memory with a memory architecture optimized for fast, low-latency random access (vs. fast consecutive address access) MirrorBit ® Cypress NVM cell technology with two localized electron storage locations to provide two data bits per cell, effectively doubling the NOR Flash Memory density Double-Data-Rate (DDR) A mode of data transfer in which data is transferred twice per clock cycle Read Bandwidth The measurement of how fast data can be read from a memory, expressed in bytes per second Terms of Art

3. 3 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Additional NOR Flash Memory Terms HyperBus™ A high-bandwidth, 12-signal interface that transfers information over 8 I/O signals at double data rate (DDR), delivering up to 333 MBps HyperFlash™ A Cypress NOR Flash Memory product family that offers higher bandwidth than Quad SPI NOR Flash Memory with one-third the number of pins of parallel NOR Flash Memory Serial Peripheral Interface (SPI) An industry-standard, low-pin-count interface used in embedded systems that enables synchronous data exchange (1 bit per cycle) between a master and slave device(s) Quad SPI An industry standard, high-bandwidth, low-pin-count interface that simultaneously uses a four-wire SPI interface to enable faster data transactions Soft Error A data error caused by background radiation Error-Correcting Code (ECC) Data encoded with extra “parity” bits to detect and correct bit errors Failures-in-Time (FIT) per Megabit of Data (FIT/Mb) The projected failure rate of a device where one FIT/Mb equals one failure per billion device hours per megabit of data Terms of Art DQ0 – DQ7 CK# RWDS 1 CK CS# Memory or Peripheral Controller 1 Read Write Data Strobe I/O Cypress HyperBus Interface (12 pins)

4. 4 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Additional NOR Flash Memory Terms Dynamic Random Access Memory (DRAM) A volatile memory that stores each bit of data on a storage capacitor that must be constantly refreshed to keep its charge HyperRAM™ A self-refresh DRAM with a HyperBus interface Program/Erase The operation required to change a NOR Flash Memory cell state from “1” to “0” or from “0” to “1”, respectively Sector A physical block of memory locations with consecutive addresses (e.g., a 256KB Sector in a 256Mb memory) Sector Erase The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming Chip Erase The operation in which all memory cells in the NOR Flash Memory array are Erased prior to Programming Terms of Art

5. 5 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) The Highest-Performance Systems Need Fast, Low-Pin-Count Memories The highest-performance systems in a broad range of market segments require NOR Flash Memory to access Program Memory and data as fast as possible Customers in these segments require fast, low-pin-count NOR Flash memories with: The highest Read Bandwidth to enable the fastest boot time 1 for instant-on 2 requirements A low-pin-count interface to reduce package size and PCB cost High reliability and low FIT/Mb rates A higher operating temperature range for systems with small enclosures and reduced airflow Designers of the highest-performance systems require the fastest low-pin-count NOR Flash Memory Communication Market Vision Automotive Instrument Cluster by Mercedes Benz Automotive Consumer Router by Cisco Systems Digital Single-Lens-Reflex Camera by Nikon 1 The time required for a system to complete automatic execution of initialization instructions stored in an NVM 2 The immediate availability of a system for user input right after being powered on

6. 6 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Cypress: No. 1 in NOR Flash, SRAM, NVRAM Comparison to Competitors’ Memory Product Portfolios Cypress has the broadest portfolio of high-performance memories for embedded systems 1 A Cypress NOR Flash Memory product family that offers higher bandwidth than Quad SPI NOR with one-third the number of pins of parallel NOR Flash Memory 2 Error-correcting code 3 Failures In Time (billion hours) 4 Ferroelectric RAM Market Positioning 5 Nonvolatile SRAM 6 NVM that provides direct, fast access to read and write to any memory location in any random order 7 A product family from Cypress subsidiary AgigA Tech that merges NAND Flash, DRAM and an ultracapacitor power source into a Nonvolatile Memory system Product CategoryCypress Competitors Performance Advantage Metrics ISSI MicronWinbondMacronix Fujitsu No. 1 NOR Flash HyperFlash™ 1  Highest Read Bandwidth333 MBps Parallel NOR Flash Highest Read Bandwidth Fastest Program/Erase 102 MBps Serial NOR Flash Highest Read Bandwidth Fastest Program/Erase 160 MBps No. 1 SRAM QDR ® -IV Synchronous SRAM  Highest RTR (random transaction rate) 2.1 GT/s Asynchronous SRAM with ECC 2  Highest reliability<0.1 FIT 3 MicroPower™ SRAM Lowest standby current1.5 µA No. 1 NVRAM Serial F-RAM™ 4  Lowest standby current100 µA Parallel nvSRAM 5 Fastest NVRAM 6 20 ns AGIGARAM ® 7 Highest-density NVRAM 6 16GB

7. 7 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) NVM Problems Designers Face 1. The highest-performance systems require the highest Read Bandwidth to access Program Memory Low Read Bandwidth not only increases boot time 1, but also slows execution of CPU instructions during operation Traditional 256Mb Quad SPI NOR Flash Memory products have Read Bandwidth as low as 54 MBps 2. They also require low-pin-count interfaces (<25 pins) to reduce system cost High-pin-count interfaces require additional signal layers on PCBs increasing cost Traditional 256Mb parallel NOR Flash Memory requires a 56-pin package (280 mm 2 ) with many control and data pins 3. They must have high system reliability Single-bit Soft Error data corruption cannot be tolerated in high-reliability systems requiring <1 FIT Traditional 256Mb Quad SPI NOR Flash Memory products do not support on-chip ECC to correct single-bit Soft Errors 4. They also require components that support higher temperature ranges Smaller enclosures with reduced airflow require components that operate at higher temperatures Traditional 256Mb Quad SPI NOR Flash Memory products are limited to +85ºC or +105ºC operation Cypress’s 256Mb HyperFlash solves these problems by providing: A DDR mode with up to 166-MHz and 333-MBps Read Bandwidth A low-pin-count, 48-mm 2 24-ball package sharing a common footprint with Quad SPI and Dual Quad SPI simplifies board layout On-chip ECC to provide a FIT rate <0.1 FIT per device An extended operating temperature range of -40ºC to +125ºC Design Problems Cypress offers the 256Mb HyperFlash for the highest-performance systems, the industry’s fastest, low-pin-count NOR Flash Memory with high reliability and extended temperature range 1 The time required for a system to complete automatic execution of instructions stored in an NVM on startup

8. 8 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Cypress HyperFlash: A Better Solution Cypress Solution Cypress’s HyperFlash NOR Flash Memory combines the industry’s highest Read Bandwidth... To enable the highest- performance systems Automotive Instrument Cluster by Visteon DDR Quad SPI Page Mode Parallel Hyper- Flash SPI With one of the lowest-pin-counts available... Read Bandwidth (MBps)Pins for Data Transfer (# of Pins) 1 Pin count for a 256Mb parallel device DDR Quad SPI Page Mode Parallel 1 Hyper- Flash SPI

9. 9 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Universal Low-Pin-Count Footprint Good Solution: Single-Quad SPI NOR Flash Memory 80 MBps, 128Mb to 1Gb RESET#/ RFU VSSVCCRFU 1 SCK RFU 1 CS#RFU 3 RFU 1 IO0IO1 IO2 RFU 1 VIO/RFU RFU 1 IO3 RFU 1 1 RFU: Reserved for future use; no device signal is currently connected to the package connector but there is potential future of the of the connecter for a signal 2 RSTO#: Reset output, this is an optional pin and not mandatory for data transactions 3 INT#: Interrupt output, this is an optional pin and not mandatory for data transactions 160 MBps, 256Mb to 1Gb Better Solution: Dual-Quad SPI NOR Flash Memory RESET#/ RFU VSSVCCRFU 1 SCK2 CS2# SCK1 VSS CS1#RFU 1 IO4RFU 1 IO0IO1 IO2 IO7IO6IO5VIO RFU 1 IO3 VSS RESET# 4 VSSVCCRFU 1 RSTO# 2 CK# 5 RFU 1 CK 5 VSSQ CS# 6 RWDS 7 DQ4VCCQDQ0DQ1 DQ2 DQ7DQ6DQ5VCCQ INT# 3 DQ3 VSSQ 333 MBps,128Mb to 512Mb Best Solution: HyperFlash™ Memory The Cypress HyperFlash NOR Flash Memory offers scalable performance and density in the same package footprint Cypress Solution 4 RESET#: Hardware reset, this is an optional pin and not mandatory for data transactions 5 CK/CK#: Differential clock pair 6 CS#: Chip select 7 RWDS: Read Write Data Strobe I/O Pins required for Single Quad SPI Additional pins required for Dual-Quad SPI Additional pins required for HyperFlash Mandatory pins for data transactions:

10. 10 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) FeatureS26KS256SS25FS256SN25Q256AMX25U25635F Interface HyperBusQuad SPI I/O Pin Count 8444 Clock Rate (DDR) 166 MHz80 MHz54 MHzNot Supported Read DDR Bandwidth (max) 333 MBps80 MBps 1 54 MBps 1 Not Supported Program Time (512B) 2 0.475 ms 1.0 ms 3 2.0 ms 3 Sector Erase Time (256KB) 2 930 ms 1400 ms 4 1600 ms 4 Chip Erase Time 2 110 s120 s240 s200 s Temperature Range -40ºC to +125ºC-40ºC to +105ºC-40ºC to +85ºC Cypress 1.8-V 256Mb (KS256S) HyperFlash Memory vs. Competition’s 1 Calculated using DDR clock rate 2 Conditions: 25ºC and V CC 3.0 V, 100k minimum endurance 3 Parts do not support 512B Programming. Program time is calculated using two 256B Program operations. 4 Parts do not support 256KB Sector Erase. Erase time is calculated using four 64KB Sector Erase operations. Competitive Comparison

11. 11 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Sampling: September 2015 Production:October 2015 Cypress’s 1.8-V 256Mb (KS256S) HyperFlash Memory Automotive instrument cluster Automotive infotainment Communication equipment Highest-performance consumer products Applications Operating voltage range: 1.70 V to 1.95 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 (min) 20-year data retention at +55ºC (typical) Initial access time: 96 ns 4 Clock rate: 166 MHz with 333 MBps Read Bandwidth Program 1 time (512B): 475 µs (typical) Sector Erase 2 time (256KB): 930 ms (typical) On-Chip ECC: Single-bit Soft Error 5 correction Industrial temp range (AEC-Q100 optional): -40ºC to +85ºC Industrial-plus temp range (AEC-Q100 optional): -40ºC to +105ºC Extended temp range 6 (AEC-Q100 optional): -40ºC to +125ºC Package: 24-ball BGA 7 6 mm x 8 mm Features Datasheet: S26KS256SS26KS256S Collateral Block Diagram Availability 5 A data error caused by background radiation 6 Endurance for devices supporting extended temperature range is 10,000 cycles min 7 Ball Grid Array (BGA) supports a 1-mm ball pitch 8 Read Write Data Strobe I/O 9 Hardware reset; not a mandatory signal for data transaction 10 Interrupt output; not a mandatory signal for data transaction 11 Reset output; not a mandatory signal for data transaction Product Overview 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming 3 The number of times a NOR Flash Memory Sector can be Programmed or Erased before it wears out 4 Following the initial read access time, a byte of data is transferred on each clock edge. At 166 MHz, the continuous data rate is 333 MBps 1.8-V 256Mb HyperFlash Memory DQ0 – DQ7 I/O Control Logic Y Decoder Data Path Array CK# RESET# 9 CK CS# RSTO 11 INT# 10 8 25 256 RWDS 8 Hyper– Bus X Decoder Embedded Voltage Control

12. 12 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) HyperFlash S26KS-S 1 65 nm, 1.8 V HyperFlash S26KL-S 1 65 nm, 3.0 V HyperRAM S27KS-1 2 63 nm, 1.8 V HyperRAM S27KL-1 2 63 nm, 3.0 V HyperFlash and HyperRAM Portfolio 256Mb 96 ns / 166 MHz * I, A, V, B, N 4, M 4 512Mb 96 ns / 166 MHz * I, A, V, B, N 4, M 4 128Mb 96 ns / 166 MHz * I, A, V, B, N 4, M 4 Q415 Q315 1Gb 3 96 ns / 166 MHz * I, A, V, B, N, M 256Mb 96 ns / 100 MHz * I, A, V, B, N 4, M 4 512Mb 96 ns / 100 MHz * I, A, V, B, N 4, M 4 128Mb 96 ns / 100 MHz * I, A, V, B, N 4, M 4 1Gb 3 96 ns / 100 MHz * I, A, V, B, N, M Q315 64-128Mb ≥256Mb 512Mb 3 Contact Sales 64Mb 36 ns / 166 MHz * I, A, V, B 512Mb 3 Contact Sales 64Mb 36 ns / 100 MHz * I, A, V, B 128Mb Contact Sales 128Mb Contact Sales 256Mb 3 Contact Sales 256Mb 3 Contact Sales Q315Q415 Density Initial Access / DDR Clock * Temp Range * C = Commercial: -0ºC to +70ºC I = Industrial: -40ºC to +85ºC A = Industrial, AEC-Q100: -40ºC to +85ºC V = Industrial-plus: -40ºC to +105ºC B = Industrial-plus, AEC-Q100: -40ºC to +105ºC N = Extended: -40ºC to +125ºC M = Extended, AEC-Q100: -40ºC to +125ºC 1 S26 = HyperFlash 2 S27 = HyperRAM 3 S70 series (stacked die) 4 Contact sales DevelopmentConceptProductionSampling QQYY Status Availability EOL (Last-Time-Ship) Roadmap

13. 13 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Here’s How to Get Started 1. Download our datasheet: Cypress KL/KS DatasheetCypress KL/KS Datasheet 2. Download our App Note: HyperFlash Programmer’s GuideHyperFlash Programmer’s Guide 3. Contact Sales for more informationContact Sales Automotive Infotainment System by Hyundai Getting Started Switch by Cisco

14. 14 Appendix 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) APPENDIX

15. 15 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Appendix Table of Contents SlideTopicDescription 19References and LinksA list of links to key documents 201.8-V 128Mb (KS128S) Product OverviewA product overview of the 1.8-V 128Mb part 213-V 128Mb (KL128S) Product OverviewA product overview of the 3-V 128Mb part 223-V 256Mb (KL256S) Product OverviewA product overview of the 3-V 256Mb part 231.8-V 512Mb (KS512S) Product OverviewA product overview of the 1.8-V 512Mb part 243-V 512Mb (KL512S) Product OverviewA product overview of the 3-V 512Mb part 25Part Selector GuideThe part number decoder for these NOR Flash Memory families 261.8-V 128Mb Competitive Comparison SlideThe Competitive Comparison version for the 1.8-V 128Mb parts 273-V 128Mb Competitive Comparison SlideThe Competitive Comparison version for the 3-V 128Mb parts 283-V 256Mb Competitive Comparison SlideThe Competitive Comparison version for the 3-V 256Mb parts 291.8-V 512Mb Competitive Comparison SlideThe Competitive Comparison version for the 1.8-V 512Mb part 303-V 512Mb Competitive Comparison SlideThe Competitive Comparison version for the 3-V 512Mb part 31Scripted EmailA scripted email for sales to send to customers

16. 16 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) References and Links S26KL/KS-S datasheet: Cypress KL/KS datasheetCypress KL/KS datasheet App note: HyperFlash Programmer’s GuideHyperFlash Programmer’s Guide Website: KL/KS websiteKL/KS website Design models: Contact SalesContact Sales Drivers and software to accelerate your design cycle: Drivers and softwareDrivers and software Hardware development tools: Contact SalesContact Sales Product selector guide: Flash Product Selector GuideFlash Product Selector Guide Product roadmap: HyperFlash PortfolioHyperFlash Portfolio References and Links

17. 17 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Sampling:August 2015 Production:October 2015 Cypress 1.8-V 128Mb (KS128S) HyperFlash Memory Automotive instrument cluster Automotive infotainment Communication equipment Highest-performance consumer products Applications Operating voltage range: 1.70 V to 1.95 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 (min) 20-year data retention at +55ºC (typical) Initial access time: 96 ns 4 Clock rate: 166 MHz with 333 MBps Read Bandwidth Program 1 time (512B): 475 µs (typical) Sector Erase 2 time (256KB): 930 ms (typical) On-Chip ECC: Single-bit Soft Error 5 correction Industrial temp range (AEC-Q100 optional): -40ºC to +85ºC Industrial-plus temp range (AEC-Q100 optional): -40ºC to +105ºC Extended temp range 6 (AEC-Q100 optional): -40ºC to +125ºC Package: 24-ball BGA 7 6 mm x 8 mm Features Datasheet: S26KS128SS26KS128S Collateral Block Diagram Availability 5 A data error caused by background radiation 6 Endurance for devices supporting extended temperature range is 10,000 cycles min 7 Ball Grid Array (BGA) supports a 1-mm ball pitch 8 Read Write Data Strobe I/O 9 Hardware reset; not a mandatory signal for data transaction 10 Interrupt output; not a mandatory signal for data transaction 11 Reset output; not a mandatory signal for data transaction Product Overview 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming 3 The number of times a NOR Flash Memory Sector can be Programmed or Erased before it wears out 4 Following the initial read access time, a byte of data is transferred on each clock edge. At 166 MHz, the continuous data rate is 333 MBps 1.8-V 128Mb HyperFlash Memory DQ0 – DQ7 I/O Control Logic Y Decoder Data Path Array CK# RESET# 9 CK CS# RSTO 11 INT# 10 8 24 256 RWDS 8 Hyper– Bus X Decoder Embedded Voltage Control

18. 18 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Sampling:July 2015 Production:September 2015 Cypress 3-V 128Mb (KL128S) HyperFlash Memory Automotive instrument cluster Automotive infotainment Communication equipment Highest-performance consumer products Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 (min) 20-year data retention at +55ºC (typical) Initial access time: 96 ns 4 Clock rate: 100 MHz with 200 MBps Read Bandwidth Program 1 time (512B): 475 µs (typical) Sector Erase 2 time (256KB): 930 ms (typical) On-Chip ECC: Single-bit Soft Error 5 correction Industrial temp range (AEC-Q100 optional): -40ºC to +85ºC Industrial-plus temp range (AEC-Q100 optional): -40ºC to +105ºC Extended temp range 6 (AEC-Q100 optional): -40ºC to +125ºC Package: 24-ball BGA 7 6 mm x 8 mm Features Datasheet: S26KL128SS26KL128S Collateral Block Diagram Availability 5 A data error caused by background radiation 6 Endurance for devices supporting extended temperature range is 10,000 cycles min 7 Ball Grid Array (BGA) supports a 1-mm ball pitch 8 Read Write Data Strobe I/O 9 Hardware reset; not a mandatory signal for data transaction 10 Interrupt output; not a mandatory signal for data transaction 11 Reset output; not a mandatory signal for data transaction 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming 3 The number of times a NOR Flash Memory Sector can be Programmed or Erased before it wears out 4 Following the initial read access time, a byte of data is transferred on each clock edge. At 100 MHz, the continuous data rate is 200 MBps Product Overview 3-V 128Mb HyperFlash Memory DQ0 – DQ7 I/O Control Logic Y Decoder Data Path Array RESET# 9 CK CS# RSTO 11 INT# 10 8 24 256 RWDS 8 Hyper– Bus X Decoder Embedded Voltage Control

19. 19 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Sampling:Now Production:September 2015 Cypress 3-V 256Mb (KL256S) HyperFlash Memory Automotive instrument cluster Automotive infotainment Communication equipment Highest-performance consumer products Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 (min) 20-year data retention at +55ºC (typical) Initial access time: 96 ns 4 Clock rate: 100 MHz with 200 MBps Read Bandwidth Program 1 time (512B): 475 µs (typical) Sector Erase 2 time (256KB): 930 ms (typical) On-Chip ECC: Single-bit Soft Error 5 correction Industrial temp range (AEC-Q100 optional): -40ºC to +85ºC Industrial-plus temp range (AEC-Q100 optional): -40ºC to +105ºC Extended temp range 6 (AEC-Q100 optional): -40ºC to +125ºC Package: 24-ball BGA 7 6 mm x 8 mm Features Datasheet: S26KL256SS26KL256S Collateral Block Diagram Availability 5 A data error caused by background radiation 6 Endurance for devices supporting extended temperature range is 10,000 cycles min 7 Ball Grid Array (BGA) supports a 1-mm ball pitch 8 Read Write Data Strobe I/O 9 Hardware reset; not a mandatory signal for data transaction 10 Interrupt output; not a mandatory signal for data transaction 11 Reset output; not a mandatory signal for data transaction 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming 3 The number of times a NOR Flash Memory Sector can be Programmed or Erased before it wears out 4 Following the initial read access time, a byte of data is transferred on each clock edge. At 100 MHz, the continuous data rate is 200 MBps Product Overview 3-V 256Mb HyperFlash Memory DQ0 – DQ7 I/O Control Logic Y Decoder Data Path Array RESET# 9 CK CS# RSTO 11 INT# 10 8 25 256 RWDS 8 Hyper– Bus X Decoder Embedded Voltage Control

20. 20 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Sampling:Now Production:September 2015 Cypress 1.8-V 512Mb (KS512S) HyperFlash Memory Automotive instrument cluster Automotive infotainment Communication equipment Highest-performance consumer products Applications Operating voltage range: 1.70 V to 1.95 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 (min) 20-year data retention at +55ºC (typical) Initial access time: 96 ns 4 Clock rate: 166 MHz with 333 MBps Read Bandwidth Program 1 time (512B): 475 µs (typical) Sector Erase 2 time (256KB): 930 ms (typical) On-Chip ECC: Single-bit Soft Error 5 correction Industrial temp range (AEC-Q100 optional): -40ºC to +85ºC Industrial-plus temp range (AEC-Q100 optional): -40ºC to +105ºC Extended temp range 6 (AEC-Q100 optional): -40ºC to +125ºC Package: 24-ball BGA 7 6 mm x 8 mm Features Datasheet: S26KS512SS26KS512S CollateralAvailability 5 A data error caused by background radiation 6 Endurance for devices supporting extended temperature range is 10,000 cycles min 7 Ball Grid Array (BGA) supports a 1-mm ball pitch 8 Read Write Data Strobe I/O 9 Hardware reset; not a mandatory signal for data transaction 10 Interrupt output; not a mandatory signal for data transaction 11 Reset output; not a mandatory signal for data transaction 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming 3 The number of times a NOR Flash Memory Sector can be Programmed or Erased before it wears out 4 Following the initial read access time, a byte of data is transferred on each clock edge. At 166 MHz, the continuous data rate is 333 MBps Product Overview 1.8-V 512Mb HyperFlash Memory Block Diagram DQ0 – DQ7 I/O Control Logic Y Decoder Data Path Array CK# RESET# 9 CK CS# RSTO 11 INT# 10 8 26 256 RWDS 8 Hyper– Bus X Decoder Embedded Voltage Control

21. 21 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) Sampling: Now Production:September 2015 Cypress 3-V 512Mb (KL512S) HyperFlash Memory Automotive instrument cluster Automotive infotainment Communication equipment Highest-performance consumer products Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 (min) 20-year data retention at +55ºC (typical) Initial access time: 96 ns 4 Clock rate: 100 MHz with 200 MBps Read Bandwidth Program 1 time (512B): 475 µs (typical) Sector Erase 2 time (256KB): 930 ms (typical) On-Chip ECC: Single-bit Soft Error 5 correction Industrial temp range (AEC-Q100 optional): -40ºC to +85ºC Industrial-plus temp range (AEC-Q100 optional): -40ºC to +105ºC Extended temp range 6 (AEC-Q100 optional): -40ºC to +125ºC Package: 24-ball BGA 7 6 mm x 8 mm Features Datasheet: S26KL512SS26KL512S Collateral Block Diagram Availability 5 A data error caused by background radiation 6 Endurance for devices supporting extended temperature range is 10,000 cycles min 7 Ball Grid Array (BGA) supports a 1-mm ball pitch 8 Read Write Data Strobe I/O 9 Hardware reset; not a mandatory signal for data transaction 10 Interrupt output; not a mandatory signal for data transaction 11 Reset output; not a mandatory signal for data transaction 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming 3 The number of times a NOR Flash Memory Sector can be Programmed or Erased before it wears out 4 Following the initial read access time, a byte of data is transferred on each clock edge. At 100 MHz, the continuous data rate is 200 MBps Product Overview 3-V 512Mb HyperFlash Memory DQ0 – DQ7 I/O Control Logic Y Decoder Data Path Array RESET# 9 CK CS# RSTO 11 INT# 10 8 26 256 RWDS 8 Hyper– Bus X Decoder Embedded Voltage Control

22. 22 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) HyperFlash Memory Product Selector Guide Product Selector Guide S 26XX YYY S DA B H I 02 0 Package Type: B = BGA 6x8 mm, 1.0-mm pitch Temp Range: I = Industrial (-40 º C to +85 º C) V = Industrial plus (-40 º C to +105 º C) N = Extended (-40 º C to +125 º C) Package Material: H = Low-Halogen Device Family: XX = KL 3.0-V HyperFlash Memory XX = KS 1.8-V HyperFlash Memory Performance: DA = 100 MHz DG – 133 MHz DP = 166 MHz S26KL/KS-S Part Numbering Decoder Density: YYY = 128 128Mb YYY = 256 256Mb YYY = 512 512Mb Technology: S = 65-nm MirrorBit Process Technology Model Number: 02 = 24-Ball BGA, 1mm Height 03 = DDR Center-Aligned Read Strobe, 24-Ball BGA, 1mm Height Packing Type: 0 = Tray 3 = 13″ Tape and Reel Spansion

23. 23 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) FeatureS26KS128SS25FS128SN25Q128A13W25Q128FWMX25U12835F Interface HyperBusQuad SPI I/O Pin Count 84444 Clock Rate (DDR) 166 MHz80 MHzNot Supported Read DDR Bandwidth (max) 333 MBps80 MBps 1 Not Supported Program Time (512B) 2 0.475 ms 1.0 ms 3 1.4 ms 3 1.0 ms 3 Sector Erase Time (256KB) 2 930 ms 2,800 ms 4 600 ms 4 1,400 ms 4 Chip Erase Time 2 55 s60 s120 s40 s100 s Temperature Range -40ºC to +125ºC-40ºC to +105ºC-40ºC to +125ºC-40ºC to +85 º C Cypress 1.8-V 128Mb (KS128S) HyperFlash Memory vs. Competition’s 1 Calculated using DDR clock rate with QIO 2 Conditions: 25ºC and V CC 3.0 V, 100k minimum endurance 3 Parts do not support 512B Programming. Program time is calculated using two 256B Program operations. 4 Parts do not support 256KB Sector Erase. Erase time is calculated using four 64KB Sector Erase operations Competitive Comparison

24. 24 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) FeatureS26KL128SS25FL128SN25Q128A13W25Q128FVMX25L12835F Interface HyperBusQuad SPI I/O Pin Count 84444 Clock Rate (DDR) 100 MHz80 MHzNot Supported Read DDR Bandwidth (max) 200 MBps80 MBps 1 Not Supported Program Time (512B) 2 0.475 ms0.340 ms1.0 ms 3 1.4 ms 3 1.0 ms 3 Sector Erase Time (256KB) 2 930 ms520 ms2,800 ms 4 600 ms 4 1,120 ms 4 Chip Erase Time 2 55 s33 s170 s40 s50 s Temperature Range -40ºC to +125ºC -40ºC to +85 º C Cypress 3-V 128Mb (KL128S) HyperFlash Memory vs. Competition’s 1 Calculated using DDR clock rate with QIO 2 Conditions: 25ºC and V CC 3.0 V, 100k typical endurance 3 Parts do not support 512B Programming. Program time is calculated using two 256B Program operations. 4 Parts do not support 256KB Sector Erase. Erase time is calculated using four 64KB Sector Erase operations Competitive Comparison

25. 25 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) FeatureS26KL256SS79FL256SS25FL256SN25Q256A13 Interface HyperBusDual-Quad SPIQuad SPI I/O Pin Count 8844 Clock Rate (DDR) 100 MHz80 MHz 54 MHz Read DDR Bandwidth (max) 200 MBps160 MBps 1 80 MBps 1 54 MBps 1 Program Time (512B) 2 0.475 ms0.25 ms0.5 ms1.0 ms 3 Sector Erase Time (256KB) 2 930 ms520 ms 2,800 ms 4 Chip Erase Time 2 110 s33 s66 s240 s Temperature Range -40ºC to +125ºC-40ºC to +105ºC-40ºC to +125ºC Cypress 3-V 256Mb (KL256S) HyperFlash Memory vs. Competition’s 1 Calculated using DDR clock rate with QIO 2 Conditions: 25ºC and V CC 3.0 V, 100k typical endurance 3 Parts do not support 512B Programming. Program time is calculated using two 256B Program operations. 4 Parts do not support 256KB Sector Erase. Erase time is calculated using four 64KB Sector Erase operations Competitive Comparison

26. 26 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) FeatureS26KS512SS25FS512SMT25QU512ABMX66U51235F Interface HyperBusQuad SPI I/O Pin Count 8444 Clock Rate (DDR) 166 MHz80 MHz66 MHzNot Supported Read DDR Bandwidth (max) 333 MBps80 MBps 1 67 MBps 1 Not Supported Program Time (512B) 2 0.475 ms 0.4 ms 3 2.0 ms 3 Sector Erase Time (256KB) 2 930 ms 600 ms 4 1,600 ms 4 Chip Erase Time 2 220 s 153 s200 s Temperature Range -40ºC to +125ºC-40ºC to +105ºC -40ºC to +85 º C Cypress 1.8-V 512Mb (KS512S) HyperFlash Memory vs. Competition’s 1 Calculated using DDR clock rate with QIO 2 Conditions: 25ºC and V CC 3.0 V, 100k minimum endurance 3 Parts do not support 512B Programming. Program time is calculated using two 256B Program operations. 4 Parts do not support 256KB Sector Erase. Erase time is calculated using four 64KB Sector Erase operations Competitive Comparison

27. 27 001-97754Owner: RYSU/HIIN Rev *ATech lead: MAMC 128Mb to 512Mb KL-S/KS-S HyperFlash™ Families New Product Introduction (Engineering) FeatureS26KL512SS79FL512SS25FL512SMT25QL512ABMX25L51245F Interface HyperBusDual-Quad SPIQuad SPI I/O Pin Count 88444 Clock Rate (DDR) 100 MHz80 MHz 66 MHz100 MHz Read DDR Bandwidth (max) 200 MBps160 MBps 1 80 MBps 1 67 MBps 1 100 MBps 1 Program Time (512B) 2 0.475 ms0.25 ms0.34 ms0.4 ms 3 0.5 ms 3 Sector Erase Time (256KB) 2 930 ms520 ms 600 ms 4 1,120 ms 4 Chip Erase Time 2 220 s66 s103 s153 s200 s Temperature Range -40ºC to +125ºC-40ºC to +105ºC-40ºC to +125ºC-40ºC to +105ºC-40ºC to +85 º C Cypress 3-V 512Mb (KL512S) HyperFlash Memory vs. Competition’s 1 Calculated using DDR clock rate with QIO 2 Conditions: 25ºC and V CC 3.0 V, 100k typical endurance 3 Parts do not support 512B Programming. Program time is calculated using two 256B Program operations. 4 Parts do not support 256KB Sector Erase. Erase time is calculated using four 64KB Sector Erase operations Competitive Comparison