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CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #22 – Multi-Context.

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Presentation on theme: "CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #22 – Multi-Context."— Presentation transcript:

1 CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #22 – Multi-Context FPGAs

2 Lect-22.2CprE 583 – Reconfigurable ComputingNovember 6, 2007 process (a, b, c) in port a, b; out port c; { read(a); … write(c); } Specification Line () { a = … … detach } Processor Capture ModelFPGA Partition Synthesize Interface Recap – HW/SW Partitioning Good partitioning mechanism: 1) Minimize communication across bus 2) Allows parallelism  both hardware (FPGA) and processor operating concurrently 3) Near peak processor utilization at all times (performing useful work)

3 Lect-22.3CprE 583 – Reconfigurable ComputingNovember 6, 2007 Recap – Communication and Control Need to signal between CPU and accelerator Data ready Complete Implementations: Shared memory FIFO Handshake If computation time is very predictable, a simpler communication scheme may be possible

4 Lect-22.4CprE 583 – Reconfigurable ComputingNovember 6, 2007 Informal Specification, Constraints System model Architecture design HW/SW implementation PrototypeTest Implementation Fail Success Component profiling Performance evaluation Recap – System-Level Methodology

5 Lect-22.5CprE 583 – Reconfigurable ComputingNovember 6, 2007 Outline Recap Multicontext Motivation Cost analysis Hardware support Examples

6 Lect-22.6CprE 583 – Reconfigurable ComputingNovember 6, 2007 Single Context When we have Cycles and no data parallelism Low throughput, unstructured tasks Dissimilar data dependent tasks Active resources sit idle most of the time Waste of resources Why?

7 Lect-22.7CprE 583 – Reconfigurable ComputingNovember 6, 2007 Single Context: Why? Cannot reuse resources to perform different functions, only the same functions

8 Lect-22.8CprE 583 – Reconfigurable ComputingNovember 6, 2007 Multiple-Context LUT Configuration selects operation of computation unit Context identifier changes over time to allow change in functionality DPGA – Dynamically Programmable Gate Array

9 Lect-22.9CprE 583 – Reconfigurable ComputingNovember 6, 2007 A B F0F0 F1F1 F2F2 Non-pipelined example Computations that Benefit Low throughput tasks Data dependent operations Effective if not all resources active simultaneously Possible to time-multiplex both logic and routing resources

10 Lect-22.10CprE 583 – Reconfigurable ComputingNovember 6, 2007 Computations that Benefit (cont.)

11 Lect-22.11CprE 583 – Reconfigurable ComputingNovember 6, 2007 Computations that Benefit (cont.)

12 Lect-22.12CprE 583 – Reconfigurable ComputingNovember 6, 2007 Resource Reuse Resources must be directed to do different things at different times through instructions Different local configurations can be thought of as instructions Minimizing the number and size of instructions a key to successfully achieving efficient design What are the implications for the hardware?

13 Lect-22.13CprE 583 – Reconfigurable ComputingNovember 6, 2007 Example: ASCII – Binary Conversion Input: ASCII Hex character Output: Binary value signal input : std_logic_vector(7 downto 0); signal output : std_logic_vector(3 downto 0); process (input) begin end process;

14 Lect-22.14CprE 583 – Reconfigurable ComputingNovember 6, 2007 ASCII – Binary Conversion Circuit

15 Lect-22.15CprE 583 – Reconfigurable ComputingNovember 6, 2007 Implementation #1Implementation #2 N A = 3N A = 4 Implementation Choices Both require same amount of execution time Implementation #1 more resource efficient

16 Lect-22.16CprE 583 – Reconfigurable ComputingNovember 6, 2007 Interconnect Mux Logic Reuse A ctxt  80K 2 dense encoding A base  800K 2 * Each context not overly costly compared to base cost of wire, switches, IO circuitry Question: How does this effect scale? Previous Study [Deh96B]

17 Lect-22.17CprE 583 – Reconfigurable ComputingNovember 6, 2007 DPGA Prototype

18 Lect-22.18CprE 583 – Reconfigurable ComputingNovember 6, 2007 Assume ideal packing: N active = N total /L Reminder: c*A ctxt = A base Difficult to exactly balance resources/demands Needs for contexts may vary across applications Robust point where critical path length equals # contexts Multicontext Tradeoff Curves

19 Lect-22.19CprE 583 – Reconfigurable ComputingNovember 6, 2007 In Practice Scheduling limitations Retiming limitations

20 Lect-22.20CprE 583 – Reconfigurable ComputingNovember 6, 2007 Scheduling Limitations N A (active) Size of largest stage Precedence: Can evaluate a LUT only after predecessors have been evaluated Cannot always, completely equalize stage requirements

21 Lect-22.21CprE 583 – Reconfigurable ComputingNovember 6, 2007 Scheduling Precedence limits packing freedom Freedom shows up as slack in network

22 Lect-22.22CprE 583 – Reconfigurable ComputingNovember 6, 2007 Scheduling Computing Slack: ASAP (As Soon As Possible) Schedule propagate depth forward from primary inputs depth = 1 + max input depth ALAP (As Late As Possible) Schedule propagate distance from outputs back from outputs level = 1 + max output consumption level Slack slack = L+1-(depth+level) [PI depth=0, PO level=0]

23 Lect-22.23CprE 583 – Reconfigurable ComputingNovember 6, 2007 Allowable Schedules Active LUTs (N A ) = 3

24 Lect-22.24CprE 583 – Reconfigurable ComputingNovember 6, 2007 Sequentialization Adding time slots More sequential (more latency) Adds slack Allows better balance L=4  N A =2 (4 or 3 contexts)

25 Lect-22.25CprE 583 – Reconfigurable ComputingNovember 6, 2007 Multicontext Scheduling “Retiming” for multicontext goal: minimize peak resource requirements NP-complete List schedule, anneal How do we accommodate intermediate data? Effects?

26 Lect-22.26CprE 583 – Reconfigurable ComputingNovember 6, 2007 Signal Retiming Non-pipelined hold value on LUT Output (wire) from production through consumption Wastes wire and switches by occupying For entire critical path delay L Not just for 1/L’th of cycle takes to cross wire segment How will it show up in multicontext?

27 Lect-22.27CprE 583 – Reconfigurable ComputingNovember 6, 2007 Signal Retiming Multicontext equivalent Need LUT to hold value for each intermediate context

28 Lect-22.28CprE 583 – Reconfigurable ComputingNovember 6, 2007 Logically three levels of dependence Single Context: 21 LUTs @ 880K 2 =18.5M 2 Full ASCII  Hex Circuit

29 Lect-22.29CprE 583 – Reconfigurable ComputingNovember 6, 2007 Three contexts: 12 LUTs @ 1040K 2 =12.5M 2 Pipelining needed for dependent paths Multicontext Version

30 Lect-22.30CprE 583 – Reconfigurable ComputingNovember 6, 2007 ASCII  Hex Example All retiming on wires (active outputs) Saturation based on inputs to largest stage With enough contexts only one LUT needed Increased LUT area due to additional stored configuration information Eventually additional interconnect savings taken up by LUT configuration overhead Ideal  Perfect scheduling spread + no retime overhead

31 Lect-22.31CprE 583 – Reconfigurable ComputingNovember 6, 2007 @ depth=4, c=6: 5.5M 2 (compare 18.5M 2 ) ASCII  Hex Example (cont.)

32 Lect-22.32CprE 583 – Reconfigurable ComputingNovember 6, 2007 General Throughput Mapping If only want to achieve limited throughput Target produce new result every t cycles Spatially pipeline every t stages cycle = t Retime to minimize register requirements Multicontext evaluation w/in a spatial stage Retime (list schedule) to minimize resource usage Map for depth (i) and contexts (c)

33 Lect-22.33CprE 583 – Reconfigurable ComputingNovember 6, 2007 23 MCNC circuits Area mapped with SIS and Chortle Benchmark Set

34 Lect-22.34CprE 583 – Reconfigurable ComputingNovember 6, 2007 Area v. Throughput

35 Lect-22.35CprE 583 – Reconfigurable ComputingNovember 6, 2007 Area v. Throughput (cont.)

36 Lect-22.36CprE 583 – Reconfigurable ComputingNovember 6, 2007 Reconfiguration for Fault Tolerance Embedded systems require high reliability in the presence of transient or permanent faults FPGAs contain substantial redundancy Possible to dynamically “configure around” problem areas Numerous on-line and off-line solutions

37 Lect-22.37CprE 583 – Reconfigurable ComputingNovember 6, 2007 Huang and McCluskey Assume that each FPGA column is equivalent in terms of logic and routing Preserve empty columns for future use Somewhat wasteful Precompile and compress differences in bitstreams Column Based Reconfiguration

38 Lect-22.38CprE 583 – Reconfigurable ComputingNovember 6, 2007 Create multiple copies of the same design with different unused columns Only requires different inter-block connections Can lead to unreasonable configuration count Column Based Reconfiguration

39 Lect-22.39CprE 583 – Reconfigurable ComputingNovember 6, 2007 Determining differences and compressing the results leads to “reasonable” overhead Scalability and fault diagnosis are issues Column Based Reconfiguration

40 Lect-22.40CprE 583 – Reconfigurable ComputingNovember 6, 2007 Summary In many cases cannot profitably reuse logic at device cycle rate Cycles, no data parallelism Low throughput, unstructured Dissimilar data dependent computations These cases benefit from having more than one instructions/operations per active element Economical retiming becomes important here to achieve active LUT reduction For c=[4,8], I=[4,6] automatically mapped designs are 1/2 to 1/3 single context size

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