1. 29/05/09A. Salamon – TDAQ WG - CERN1 LKr calorimeter L0 trigger V. Bonaiuto, L. Cesaroni, A. Fucci, A. Salamon, G. Salina, F. Sargeni

2. 29/05/09A. Salamon – TDAQ WG - CERN2 L0 LKr trigger L0 LKr trigger (photon veto): cluster counting with 1-2 ns time resolution Use existing hardware (NA48 and LHC) Use the NA48 analog sums (2x8 cells) and cables replacing the “old” system with a new TELL1 based system

3. 29/05/09A. Salamon – TDAQ WG - CERN3 L0 LKr trigger Use analog sums (2x8 cells) and all the cables already exist Need to design the trigger processor read-out boards 13k analog channels analog sums LKr calorimeter DAQ 864 analog channels L0 LKr trigger read-out after L0 CTP

4. 29/05/09A. Salamon – TDAQ WG - CERN4 L0 Lkr trigger: architecture Concentrator TELL1: merging, sorting 24 Front-End TELL1 Front-End TELL1: pulse reconstruction (time, position and energy) 32 analog channels (1 channel = 2x8 liquid krypton cells analog sum) 1 analog sum (supercell) = 2x8 channels 28 FE TELL1s, 5 concentrator TELL1s, 32 supercells per TELL1

5. 29/05/09A. Salamon – TDAQ WG - CERN5 FE boards: pulse reconstr (time, position, energy) TELL1 28 boards CTP L0 LKr Trigger: architecture Need to design: –one FE + ADC mezzanine –one link to connect FE and concentrator TELL1s Two 9U crates! 13248 channels for the readout  864 channels (2x8 pixel supercells) for the trigger! ADC mezz 32 supercells Concentrator boards: merging, sorting TELL1 24 ch 5 boards Receiver mezz 1 meter 32 ch

6. 29/05/09A. Salamon – TDAQ WG - CERN6 80 MHz sampling: 50 ps/bin full scale pulse -> 100 ps rms 40 MHz sampling: 100 ps/bin 1/40 full scale pulse + noise and jitter -> 700 ps rms simulation Some plots (digital simulation!!!)

7. 29/05/09A. Salamon – TDAQ WG - CERN7 FE to concentrator link I (new receiver) Use existing gbit ethernet output mezzanine and design new ethernet receiver on the concentrator Up to 24 ethernet input on the concentrator = 8 FE TELL1 (3 gbit per TELL1) 24 ethernet connector is (mechanically) difficult but possible Pros: lower design effort, bidirectional, added FPGA processing power on the receiver, flexible (same link for trigger and readout) Cons: ethernet overhead, lower bandwidth TELL1 Concentr Ethernet mezz ethernet Front-End Eth TX TELL1 NEW!!

8. 29/05/09A. Salamon – TDAQ WG - CERN8 FE to concentrator link II (new TX) Use existing optical receiver input mezzanine on the concentrator and design new ethernet + fiber optic transmitter Cons: higher design effort, monodirectional, no added FPGA processing power on the receiver Pros: no ethernet and added latency on the trigger path, higher bandwidth TELL1 Concentr Optical mezz opt fiber Front-End Eth + opt TX TELL1 NEW!!

9. 29/05/09A. Salamon – TDAQ WG - CERN9 FE to concentrator link (new TX and RX) Design a new TX with 1-2 ethernet link for the readout and 1 dedicated link for the trigger Design a new RX with 8 dedicated link for the trigger Cons: higher design effort, no added FPGA processing power on the receiver Pros: no ethernet and added latency on the trigger path, (much) higher bandwidth, bidirectional TELL1 Concentr Channel link ch link Front-End Eth + ch link TELL1 NEW!!

10. 29/05/09A. Salamon – TDAQ WG - CERN10 Channel link Up to 6.3 Gbps Up to 1.8 Gbps

11. 29/05/09A. Salamon – TDAQ WG - CERN11 3M cable 3M commercial cable: 11 shielded twisted pairs 9 twisted pairs for the FE TELL1 to concentrator TELL1 link (up to 6.3 Gbps) 2 twisted pairs for the concentrator TELL1 to FE TELL1 link (up to 1.8 / 3 Gbps)

12. 29/05/09A. Salamon – TDAQ WG - CERN12 Channel link + 3M cable data rate

13. 29/05/09A. Salamon – TDAQ WG - CERN13 RX mezzanine Schematic ongoing, PCB layout at CERN

14. 29/05/09A. Salamon – TDAQ WG - CERN14 Ethernet link for the LKr trigger TELL1 readout Our collaborators at the Tor Vergata Engineering Department are working on a development board for the ethernet readout part of the TX mezzanine ethernet

15. 29/05/09A. Salamon – TDAQ WG - CERN15 Ethernet link for the LKr trigger TELL1 readout Demo board setup, running and connected to the PC

16. 29/05/09A. Salamon – TDAQ WG - CERN16 FE ADC mezzanine Before designing the FE + ADC mezzanine we want to do some tests!!! We are preparing our test station for the Front-End mezzanine AWG 2021 -> analog sums mezzanines -> cable -> TELL1 analog mezzanine -> TELL1 Arbitrary waveform generator: AWG2021 NA48 analog sum card TELL1 TELL1 analog mezzanine STATUS: the TELL1 is up and running (boot server installed, etc), our master degree student (L. Cesaroni) is working on AWG + NA48 sum card + TELL1 ADC integration

17. 29/05/09A. Salamon – TDAQ WG - CERN17 BACKUP SLIDES

18. 29/05/09A. Salamon – TDAQ WG - CERN18 The TELL1 board LHCb general purpose data acquisition board 5 user programmable FPGAs, large on-board DDR memories mezzanines for 4 x 1 gbit ethernet output analog mezzanine 16 x 10 bit Stratix FPGA 25k logic elem Stratix FPGA 40k logic elem digital mezzanine 12 x 16 bit parallel bus 32 bit @ 160 MHz output interface 4 x gbit ethernet

19. 29/05/09A. Salamon – TDAQ WG - CERN19 Pulse reconstruction (FE TELL1) Peak in space Peak in time Over threshold 7 bit reconstructed fine time Parabolic fit Peak processor (one channel) Peak finder (one channel)

20. 29/05/09A. Salamon – TDAQ WG - CERN20 Hit rates (Front-End TELL1s) Instantaneous design hit rate (Marco’s TDAQ note): 30 MHz Rate in the central region (Giuseppe’s private communication): 3 times mean hit rate Clusters of 256 liquid krypton cells (conservative) All hits generate a shower (conservative) ( 30 MHz / 28 ) x 3 = 3.2 ( 30 MHz / 28 ) x 3 / 8 = 0.4 TOTAL RATE = 10.8 MHz vs 64 bit/cluster over 3 gbit eth links

21. 29/05/09A. Salamon – TDAQ WG - CERN21 Hit rates (PP FPGA = ¼ TELL1) Same assumptions Fast communication between PP FPGAs in the same TELL1 -> rate reduction ( 30 MHz / 28 ) x 3 / 8 = 0.4 TOTAL RATE = 4.8 MHz vs 64 bit/cluster over 32b @ 160 MHz ( 30 MHz / 28 ) x 3 /4 = 0.8

22. 29/05/09A. Salamon – TDAQ WG - CERN22 Concentrator TELL1 (overlkap handling and hit rates) Maximum in the red area: the cluster is handled by the “red” TELL1 concentrator Maximum in the blue area: the cluster is handled by the “blue” TELL1 concentrator Double counting resolved at the level of the concentrator Only 4 over 8 Front-End TELL1s contribute to the output hit rate: OUTPUT RATE = (30 MHz / 28) x 3 x 4 = 12.9 MHz vs 64 bit/cluster over 3 gbit eth links

23. 29/05/09A. Salamon – TDAQ WG - CERN23 Front-End ADC mezzanine At the moment we are preparing a test stand using an existing LHCb mezzanine New mezzanine later TELL1 28 boards CTP ADC mezz 32 supercells TELL1 24 ch 5 boards Ethernet mezz ethernet 32 ch