1. Timing waveform for an I/O bus  Determine which signals are active LOW and which are active HIGH  Are any of the signal lines multiplexed, and if so why do you think that this is the case?  By considering the timing points T1-T10 on the waveform suggest the possible relationship between the signals and explain which signals affects another and why? Timing waveform for an I/O bus  Determine which signals are active LOW and which are active HIGH  Are any of the signal lines multiplexed, and if so why do you think that this is the case?  By considering the timing points T1-T10 on the waveform suggest the possible relationship between the signals and explain which signals affects another and why?

2. T1 read-cycle begins by loading proper address and drives the W/R signal high to indicate a read-cycle. high impedance state ( = high-z).

3. T2 After the address setup time (T1,2), the control signal /REQ is used to activate the addressed peripheral module and to indicate that the data are stable. bus is in the high impedance state ( = high-z).

4. T3 The addressed module asserts the /RDYCLK signal in order to indicate the activation. The peripheral reaction time T2,3 is strictly specified by the use of special circuits.

5. T4 The master drives the data lines. T5 The data are stable.

6. T6 The peripheral module deasserts the /RDYCLK line in order to indicate, that the data are read and the READY signal is activated for the next operation T7 The cycle ends by deasserting the /REQ signal.

7. T8 data-bus driver.is disabled. The data are invalid. T9 The address bus is released. T10 The data bus is in the high impedance state ( = high-z).