1. SRTSC A LabVIEW based Test and Hardware Configuration System for SRS Volkan Gezer Eskisehir Osmangazi University & CERN

2. Aim of SRTCS Test of SRS electronics cards for production conformance Configuration or Reconfiguration of parameters To be used both for production (PRISMA) and end-users Scope: FEC card, ADC card, (Hybrid) More SRS cards to be added Volkan Gezer - volkan.gezer@cern.ch2SRTCS

3. SRS test infrastructure Laptop / PC with LabVIEW 2010 and ethernet cable SRS Crate-HP or desktop ATX –SRS power 1 FEC Reference card with 1000BASE-T SFP-ethernet plugin 1 SRS ADC Reference card 1 SRS CTF Reference card 1 HDMI cable A-D* 2 APV hybrids V4 (Master & Slave) + SAMTEC flat cable 1 DTC link cable (special) 1 Ethernet Cross cable 1 Coaxial cable 50 OHM 1 LVDS – RJ45 cable (special) 1 Digital Voltmeter 1 Xilinx USB programmer head Xilinx iMPACT programming tool (free WEB version) SRS FEC Firmware (latest version) Volkan Gezer - volkan.gezer@cern.ch3 * Older versions of hybrids need special HDMI cable

4. SRTCS Test setup overview Volkan Gezer - volkan.gezer@cern.ch4 FECADC chip CTF Ethernet SRTCS ATX power SRS crate HDMI cable Clock and trigger generation FPGA Loop cable diff LVDS cable Operator dtc cable

5. SRTCS Jumpers and Microswitches Volkan Gezer - volkan.gezer@cern.ch5 Jumper positions Microswitches on ADC Don’t start tests before verification of these

6. SRTCS Firmware Programming Volkan Gezer - volkan.gezer@cern.ch6 lamp must be green! Xilinx iMPACT Program

7. Test overview* 1. Basic tests: – Voltages are good – FPGA works – Connectors work (soldered etc…) 2. Functionality tests – SRTCS and Firmware Volkan Gezer - volkan.gezer@cern.ch7SRTCS * Tests may not cover 100% functionality in first version

8. SRTCS features* Full range of conformance tests User-friendly error reporting Auto-increment serial number Auto MAC address generation and programming Fully documented buttons with context help Save as HTML and/or Print Reports with success or fail messages Expert mode, enabling manual commands and error decoding. Volkan Gezer - volkan.gezer@cern.ch8SRTCS * beta version 1.0a

9. SRTCS User Interface Volkan Gezer - volkan.gezer@cern.ch9 Run button on toolbar SRTCS

10. FEC Configuration Volkan Gezer - volkan.gezer@cern.ch10 Password protected increment

11. FEC: MAC address allocation Auto-generation based on serial number Two types of allocation: – 1k CERN Range: SRS-MAC = 08-00-30-F2-00-00 … 08-00-30-F2-FF-FF – External User: Xilinx MAC range (to be discussed), starting with 00-0A-35 Volkan Gezer - volkan.gezer@cern.ch11SRTCS

12. Done Volkan Gezer - volkan.gezer@cern.ch12SRTCS Finalize Configuration button

13. FEC Configuration Report Volkan Gezer - volkan.gezer@cern.ch13SRTCS Should be printed after each successful test and configuration

14. SRTCS A. FEC Card Test Volkan Gezer - volkan.gezer@cern.ch14 Dialog appears for each test button

15. A.1. Setup of FEC Front Panel Tests (with Reference CTF) Volkan Gezer - volkan.gezer@cern.ch15 CTF Switch in Internal Clock and Trigger Mode SRTCS

16. A.2. DTC Link Cross Cable Between J1 and J2 1  (orange white)  4 2  (orange)  5 3  (green white)  7 4  (blue)  1 5  (blue white)  2 6  (green)  8 7  (brown white)  3 8  (brown)  6 Volkan Gezer - volkan.gezer@cern.ch16 J1 J2 Cross cable pinout* SRTCS *standard ethernet cross cable needed for test button “check J1-J2“

17. A.3. CTF link cable between CTF OUT and J2 on FEC card & LVDS Clock Cable Volkan Gezer - volkan.gezer@cern.ch17 8  White-orange  7 7  Orange  8 6  White-green  2 (CLK-) 5  Blue  4 4  White-blue  5 3  Green  1 (Clk+) 2  White-brown  6 (Trg-) 1  Brown  3 (Trg+) J2 CTF OUT CTF –J2 special cable pinout SRTCS needed for CTF clock test button LVDS In

18. SRTCS B. ADC Card Test Volkan Gezer - volkan.gezer@cern.ch18

19. B.1. Setup of ADC Card Test requires reference CTF, FEC, and 2 Hybrids Volkan Gezer - volkan.gezer@cern.ch19SRTCS

20. C. Hybrid Test (planned test screen) Volkan Gezer - volkan.gezer@cern.ch20 JTAG link to Hybrids OK All channels work Chip Works Pedestal Values are OK Register configuration OK Incoming chip data OK

21. SRTCS Error reporting Volkan Gezer - volkan.gezer@cern.ch21SRTCS Error 1 occurred at srtcs.vi Possible reason(s): LabVIEW: An input parameter is invalid. For example if the input is a path, the path might contain a character not allowed by the OS such as ? or @. ========================= NI-488: Command requires GPIB Controller to be Controller-In-Charge.

22. D. Expert -> Expert Tab Volkan Gezer - volkan.gezer@cern.ch22SRTCS

23. Thank you for listening. Your suggestions are welcome Volkan Gezer volkan.gezer@cern.ch volkangezer@gmail.com Volkan Gezer - volkan.gezer@cern.ch23SRTCS

24. Backup Volkan Gezer - volkan.gezer@cern.ch24SRTCS

25. D. Expert -> UDP Flow Tab Volkan Gezer - volkan.gezer@cern.ch25 6519: FFFFFFFFAAAAFFFF00000000000000000000000000000001000000000002000000000000000300000000000000040000 0000000050000000000000006000000FF00000000000000FF 6263: FFFFFFFFAAAAFFFF000000000000001000000064000000110000003C000000120000002200000013000000220000001400000022000 0001500000037000000160000000A00000017000000000001800000064000000190000001E0000001A0000003C0000001B00000028 0000001C000000EF0000001D000000FE0000 00010000001900000002000000840000000300000004 6039: FFFFFFFFAAAAFFFF0000000000000000000000030000000100000005000000080000FFFF0000000F00000001 SRTCS

26. ISE iMPACT and Programming Volkan Gezer - volkan.gezer@cern.ch26SRTCS http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm Free version available: You need to turn FEC on for status led of the programmer go green

27. FEC Voltage test points Volkan Gezer - volkan.gezer@cern.ch27SRTCS

28. FEC backside test points Volkan Gezer - volkan.gezer@cern.ch28SRTCS

29. ADC Voltage test points Volkan Gezer - volkan.gezer@cern.ch29SRTCS

30. SRTCS Block Diagram Volkan Gezer - volkan.gezer@cern.ch30SRTCS

31. SRTCS: To do Volkan Gezer - volkan.gezer@cern.ch31