1. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20091 SVT- Status Update on R&D activities for TDR X SuperB General Meeting Workshop SLAC – Oct. 6-9, 2009 Giuliana Rizzo Universita’ & INFN Pisa

2. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20092 SVT-Update R&D work organized to prepare a baseline for TDR with: Layer0 (small pitch/thin/fast/rad hard) based on hybrid pixels Hot issues to match SuperB specs: 1.50x50  m 2 pitch + fast readout 2.Light pixel module support & cooling 3.Pixel module interfaces (Al Bus & fast links) Layer1-Layer5 similar to BaBar SVT –Layout Optimization & Design Continue R&D on thin pixel options –MAPS with new cell under test: LAB, testbeam, rad. test Background studies  impact on detector & beam pipe design SVT Mechanics & fast removal (covered in Mike Sullivan’s talk) Fast Simulation studies (DGWG & FastSim sessions)

3. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20093 Agenda of the SVT Parallels SVT I - Tuesday 6 Oct. 16-17:30 –Introduction – G. Rizzo –Update on MAPS activities & FE4D32x128 chip analog cell - G. Traversi (PV/BG) –Hybrid pixel readout chip: FE4D32x128 A. Gabrielli (BO) SVT II Wednesday 7 Oct 8:30-10:00 –First results on analog MAPS from July CERN Testbeam – S. Bettarini (PI) –Update on pixel bus & pixel module interfaces – M. Citterio (MI) –Update on Pixel Sensor design – G. Dalla Betta (TN) –Strip layer design: first considerations – L. Vitale (TS) SVT III - Wednesday 7 Oct 10:30-12:00 –UK Activities & Plans – F. Wilson (RAL) –Layer0 support & SVT Mechanics– F. Bosi (PI) –Update on SVT Background evaluation – R. Cenci (PI)

4. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20094 Thanks to the effort of all the designers (PV/BG-BO-PI) Fabio Morsani is closing the layout as we speak! Plans for Hybrid Pixel (I) Produce & test a prototype front-end chip for high resistivity pixels with 50x50 um 2 pitch & fast enough readout (high background) - Front-end Chip & Pixel sensor matrix layout almost completed both in production from Oct ‘’09 - FE chip: ST 130 nm process, Sensors: FBK-IRST - Sensor + chip bump-bonding next spring (IZM-Berlin)  Testbeam Sept. 2010. Cell Layout FE chip Layout (32x128) – preliminary 50  m Details on the FE chip and pixel sensor Matrix: G.Traversi(PV/BG),A.Gabrielli(BO), GF Dalla Betta (TN)

5. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20095 S/N ~ 100 for 200 um thick sensor G.Traversi(BG)

6. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20096 FE Chip architecture Data from the final barrel are sent to a common bus with a faster clock ~ 160 MHz A.Gabrielli (BO) Each readout sweeps a portion of the matrix with 60 MHz clock. Use data push readout architecture developed for MAPS chip, now optimized with target rate (100 MHz/cm2) for full chip size (~1.3 cm2) VHDL simulation: readout efficiency > 98% @ 60 MHz RDclock Space time coordinates with time granularity 0.2-5.0 us (BCO clock)

7. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20097 Pixel Sensor Matrix Layout of the sensor wafer almost completed: –Several matrix sizes 32x128  256x128 (for multichip assembly) –N-on-N: P-spray isolation on n-side, p implant on the back side Wafer thickness: 200  m (FZ, HR Si) Pixel capacitance (~ 20 fF) is dominated by the bump bond capacitance ~ 80 fF Termination structures: –Large GR on the pixel side –Multiguards on the bias side N side P side GF. Dalla Betta (TN)

8. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20098 PAD on test chip positioned to allow single chip on carrier test but also production of a multichip pixel module: - 3 chips + pixel sensor matrix + Al bus + support with integrated cooling. Pixel module 2 or more chips + sensor and Al pixel bus. Plans for Hybrid Pixel (II) Update on pixel bus & pixel module interfaces – M. Citterio Update on Layer0 support & cooling – F. Bosi

9. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 20099 Light pixel module support & cooling Light support with integrated cooling needed for pixel module: P=2W/cm 2 Carbon Fiber support with microchannel for coolant fluid developed and characterized in the Thermo-fluid-dynamics LAB in Pisa: –Total support/cooling material = 0.2-0.3% X0 CF support with microtubes glued toghether 0.28 % X0 (L=12.8 mm) F.Bosi (PI) 700  m Carbon Fiber Poltrusion Net with CF microchannel (0.2% X0)

10. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200910 Light pixel module support & cooling T(FEA)=32 0 C @ P=2W/cm 2 Prototypes characterized varying the specific input power (1-3W/cm2) Measurements confirmed FEA simulation results: T_meas=30-36 0 C @ P=2W/cm 2 Measured Temperature along the module Kapton heather Temp. probes Temp. probes - Kapton heater F.Bosi (PI)

11. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200911 Pixel Module Interfaces Light (Al/Kapton) multilayer, high speed (160 MHz) and high track density pixel bus (requirements in competition!) in prodution @ CERN shop. Delivery delayed to Oct. 23 M. Citterio (Milano) Mixed technology - Cu+optical link solution seems more affordable: –storing data on the HDI (serializer: LOC chip is a possible choice) –Short (30-50 cm) Copper link between HDI  transition card (3 Gbps) –optical link in medium rad. tolerant area: transition card  DAQ –Link test setup in progress in Milano (ready by the end of 2010)

12. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200912 New MAPS testbeam in July 2009 Results for MAPS (3x3 matrix) with analog output (pre/post irradiation 10 Mrad) Qcluster ~1040 e- for M1 (930 e- for M2) S/N~15-20 depending on the electrode geometry Efficiency~90% for both M1,2 @400e- in agreement with the measurements on digital MAPS Modest reduction in collected charge and efficiency in chip irradiated up to 10 Mrad –S/N reduction due to the increase of ENC. (30-40%) apsel3T1 July 2009 CERN Testbeam S = 1003 e- M1 - 3x3 cluster signal 120 Gev pions - after 10 Mrad M1 - chip 8 not irradiated M1 chip 24 @ 10 Mrad Efficiency Thr. e- THR < 4  Noise Not feasible S. Bettarini (Pisa)

13. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200913 Background Simulation Good progress in Back. Simulation Hit rate, Radiation Dose, equivalent fluency plots produced for all SVT layers. Machinery is now in place! Different beampipe & L0 configurations studied but rates in L0 still very high. Layer 0 with radius ~ 1.5 cm –Rate > 200 MHz/cm2 !!! –TID > 30 Mrad/yr !!! Background dominated by e+ e- pair production Rate of low momentum e+ e- hitting the beam pipe and Layer0 can be reduced increasing the B field … need to investigate carefully this option. R. Cenci (Pisa) Safety x 5

14. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200914 Strip layers design: first considerations 1. Background in Layer1 still dominated by pair production (1.0 MHz/cm 2) L1 occupancy 7.5% in 132 ns (safetyx5): –critical for the reconstruction, –FSSR2 old simulation: 98.5% efficiency with 6% occupancy, Must operate FSSR2 at its limits –Need to revise performance with simulation and continue evaluation in lab. Try to reduce pair production background 2. In the longest (L5 ~ 37 cm) strip modules, read out with FSSR2, poor performance expected due to high C load and R S. ENCtot = 2700 e- S/N = 9 Need to implement modification on the analog part of the chip –PV/BG group was the original designer of the FSSR2! Front end chip candidate: FSSR2 from BTEV 1.Is FSSR2 fast enough to stand the bkg rate in L1-L2? 2.Is its signal-to-noise adequate for the long external layers? L. Vitale (TS)

15. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200915 News from UK UK groups (RAL/QMUL) interested in the SVT R&D for TDR Using the experience on MAPS devices developed for ILC they are interested in proposing a full SVT (L0-L5) based on MAPS pixel devices. From now to December they will pursue a feasibility study of application of MAPS for the full SVT: –Evaluate the impact on physics of a full SVT based on pixel modules (FastSim) –Prepare a conceptual design of a full SVT based on MAPS (SuperB requirements need to be matched) F.Wilson (RAL)

16. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200916 Conclusions Layer0 R&D is proceeding in the most critical areas: –Front-end chip, sensor, Al bus prototypes in production. –Test setup of the various components in preparation to have real measurements for the TDR...no too much contingency though. Engineering of the more “standard” part of the detector is starting (support structure & L1-L5 strip detector) … manpower is an issue especially in this area.

17. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200917 Layer0 Module Specs Key issues to demonstrate we can built it: 1.Front-end chip for high resistivity pixels 2.Multichip pixel module interfaces 3.Light Module support and cooling Link

18. G. RizzoSVT Status – SuperB Workshop, SLAC Oct 9 - 200918 SVT Mechanics (II) Very fruitful discussion with the IR designers on the main issue: easy/fast access for replacement of the Layer0 & beam pipe. –Layer0 upgrade & beam pipe at smaller radius –Brainstorming on various options –Fast removal of the entire IR beam pipe +Layer0+SVT inserting a sliding temporary Support Tube with rails for the access I.R. Model+L0 M.Sullivan I.R. model with L0 positioned F. Bosi (Pisa)