1. EE222 Winter 2013 Sung Mo (Steve) Kang Office BE235 Phone 831-459-3580 Cell 831-706-5456Office BE23531-459-3580 kang@soe.ucsc.edu C Course website http://courses.soe.ucsc.edu/courses/ee222/ http://courses.soe.ucsc.edu/courses/ee222/ Course lecture recorded http://webcast.ucsc.edu

2. Lecture No.DateSubjectReferenceNote 1Jan 8 (T)IntroductionRby-Ch1 2Jan 10 (Th)Power, Energy BasicsRby-Ch3 3Jan 15 (T)Circuit level power optimizationRby-Ch4 4Jan 17 (Th)Systems level power optimizationRby-Ch5 5Jan 22 (T)continuedRby-Ch5 6Jan 24 (Th)InterconnectsRby-Ch6 7Jan 29 (T)Clock signalingRby-Ch6 8Jan 31 (Th)Low power memoryRby-Ch7 9Feb 5 (T)Low power memoryRby-Ch9 10Feb 7 (Th)Midterm exam 11Feb 12 (T)Low power CASRby-Ch8 12Feb 14 (Th)Low power CASRby-Ch10 13Feb 19 (T)Project proposal presentation 14Feb 21 (Th)Ultra low power/voltage designRby-Ch11 15Feb 26 (T)continued 16Feb 28 (Th)Low power design flowsRby-Ch12 17Mar 5 (T)Continued 18Mar 7 (Th)Project presentation 19Mar 12 (T)Continued 20Mar 14 (Th)Course review

3. Guidelines for Course Projects Each team is consisted of 2-3 members Two members are expected to contribute equally. Project options –Selection of a major milestone paper published in a journal or a conference that addresses low power design of VLSI circuits. –Comprehensive and critical review of the paper. –If possible, propose ways to improve the technical contents. –Both proposals and final presentations will be peer reviewed by other teams.

5. The Missing Link in Constitutive Relations V = R I (Resistor) Q = CV(Capacitor) Φ = L I (Inductor) Φ = f (Q) Φ Q V I V = d/dt Φ d Φ /dt= df(Q)/dt = df(Q)/dQ. dQ/dt V= M I Memristance M=M(Q)/ I = d/dt Q

6. Nonvolatile Memristive Memory Nanotechnology enables ultra dense memory S.H. Cho, et. al., Nano Letters, 2009; New York Times, Aug. 2010 Early 1kB memory based on p-Si/a-Si/Ag by Univ. Michigan HP-Hynix collaboration on next generation memory products  High quality memristive memory chips in a few years  Expected features (compared to FLASH)  Speed: >10x. Power 5X

7. Nanostore-Based Distributed System with 3D-Stacked Memristors HP- Collocate processors and Memristor memory on chip

8. Axes of Device Requirements (Memristor)

15. Power and Energy Basics

18. required to charge the capacitor, although it will determine the charging time.

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41. Drain-voltage Induced Barrier Lowering

48. “Soft” Power Meter Ref. S. M. Kang, “Accurate simulation of power dissipation in VLSI circuits,” IEEE J. of Solid-State Circuits, pp.891-891, Oct. 1986 + P N P tree N tree Load + _ 0V R C

51. Optimal Design of a Super Buffer Ref. pp268-269, S. M. Kang and Y. Leblebici, CMOS DIGITAL CIRCUITS 3 rd ed., McGraw Hill, 2003 Super Buffer 1α