1. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon KM3NeT CLBv2 1

2. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon CLB should support 31 TDC’s 1 ns resolution “Knowledge” of absolute time (1 ns resolution) Data pushed from PMTs to Shore Station I2C: PMT-HV, Threshold, Compass, Tilt Other IO: Temp, Nano beacon, Aucoustics Firmware must be reconfigurable Low Power Low Cost Part of a scalable system (with respect to the the complete detector) Highly reliable 2

3. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon How to divide into system components Shore Station GPS DOM CLB CLB is not a separate entity! Take lower OSI layers of CLB and Shore Station both into account! Optical Network 3

4. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon Three systems briefly analyzed “Ethernet based” “White Rabbit” “Home Brew” See last Friday’s presentation: http://agenda.nikhef.nl/conferenceDisplay.py?confId=2087 4

5. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon Planning October 1, 2012 FPGA choice ◦ First we need to know what system we are going to build! ◦ This needs study… And time… December 1, 2012 TDC and Timing Verified in FPGA ◦ Planning absolutely not feasible! ◦ Again, First we need to know what system we are going to build! Q1 2014 functional CLB’s operational? ◦ Far from realistic! 5

6. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon What we need anyhow… Knowledge about DDMTD => look and learn code (this is not an easy task) ◦ from Yassir Mouden Saclay ◦ White Rabbit (http://www.ohwr.org/projects/white- rabbit/wiki)http://www.ohwr.org/projects/white- rabbit/wiki CLB Timing Loopback External PLL ◦ Study loop filter optimization TDC (in Xilinx?; ISERDES) ◦ port Albert Zwart / Yassir Mouden design 6

7. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon What we need anyhow-2… MAC ◦ Amount of Xilinx TEMACs per device is limited (Issue for Shore Station) ◦ Open Cores MAC? ◦ Most simple implementation can be made ourselves (which creates the possibility to add timing on the data link layer without corrupting (raw) Ethernet packets.  Simplifications:  no real need for Host Interface  no real need for MDIO interface (MAC PHY) 7 Doubting again since last Friday…

8. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon What we need anyhow-3… Implement interfaces: ◦ I2C and other IO (ADCs for Acoustics) Implement re-configurability Software needed! (nowhere on the current planning…) ◦ Embedded (in CLB) ◦ Test software on a “Test Shore Station” PC 8

9. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon Conclusions FPGA choice… ◦ Choose between Vendor => I guess we choose Xilinx ◦ Avoid “Vendor lock in”! ◦ Family (Virtex-6, Spartan-6, Kintex-7, Artix-7) will all do the job => buy a Kintex-7 evaluation kit and find out if we can downscale to Artix-7 eventually More important, decide between: ◦ “Ethernet based” ◦ “White Rabbit” ◦ “Home Brew” Please don’t use an operating system! ◦ Way to much for the job and it consumes lots of power and money Lets start as soon as possible to try and port/implement various code (see “What we need anyhow”) on the evaluation kit. Planning is tight, lets see how far we will come! 9

10. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon KC705 Quote from Avnet/Silica Investigate White Rabbit PTP Core ◦ See if things can be reused ◦ This got me doubting again between “Home brew” and “White Rabbit” solutions 10 Since last Friday…

11. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon Questions? Comments? 11

12. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon Backup Slides 12

13. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon FPGA choice All of us have Xilinx experience so this seems a natural choice (although the above statement is still valid). Still… design should preferably be Vendor independent as much as possible. SerDes > 1.25 Gbps Timing: SerDes must be BitSlide trick capable TDC: IO capable of handling 1 ns resolution Enough Resources ◦ memory! (Especially important when on chip CPU is used). Power ◦ Unused resources add up in “leakage” current (which is a significant amount compared to resources used). 13

14. Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon CPU Needed at all? ◦ I think it makes life and testability much easier and it is very much worth the investment (even with the home brew solution) No operating system ◦ Needs too much memory and resources while there is no (or small) advantage. Software needs to be revised anyway… External or internal in FPGA ◦ Board space / Reliability ◦ Price ◦ Power ◦ Experience so far… If internal to the FPGA then Vendor independent ◦ LEON, LM32 (Note: MicroBlaze, NIOS, Zynq and Virtex5-PPC are vendor dependent!) ◦ Select FPGA with enough:  1) Memory (RAM Blocks)  2) Logic Resources 14