1. January 21, 2011GT20101 Multicore SoC Architecture and Prototyping for Parallel ECG Processing s1150072 Yumiko Kimezawa Supervised by Prof. Abderazek Ben Abdallah Adaptive System Laboratory, The University of AIZU, Japan

2. Outline Background -PPD Algorithm study -Problems with Haga’s system -Architecture of Haga’s system Proposed new system architecture Evaluation results -Results of logic synthesis -Execution time Conclusion Future work January 21, 2011GT20102

3. Background January 21, 2011GT20103 ECG is used for diagnosis of heart disease Haga’s system processes ECG signals one single lead at a time Figure: Haga’s system architecture proposed last year ADC 1 ADC 12 FIR 1 FIR 12 Buffer ECG Signal Analysis 1:Signal reading 2:Filtering3:Analysis4:Display 12 leads External Memory Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms

4. Background January 21, 2011GT20104 ECG is used for diagnosis of heart disease Haga’s system processes ECG signals one single lead at a time Figure: Haga’s system architecture proposed last year single lead PPD Algorithm is used ADC 1 ADC 12 FIR 1 FIR 12 Buffer ECG Signal Analysis 1:Signal reading 2:Filtering3:Analysis4:Display 12 leads External Memory Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms

5. PPD Algorithm study (1/2) January 21, 2011GT20105 Period-Peaks Detection (PPD) Algorithm Figure: ECG graph

6. PPD Algorithm study (2/2) January 21, 2011GT20106 Detection of period Processing of peaks Data reading Derivation Autocorrelation Finding interval Extraction Store of results Discrimination

7. Problems with Haga’s system January 21, 2011GT20107 Haga’s system can not process ECG signals from multiple leads at a time Not high performance

8. Single lead system architectu re January 21, 2011GT20108 Raw ECG Data ROM External Memory External Memory Graphic LCD Controller Slave CPU Slave CPU Slave CPU Memory Timer Master CPU Memory Master CPU Memory Master CPU Master CPU Timer Shared Memory Shared Memory FIR Filter Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module : Data flow : Control signal : Data flow : Control signal LED Controller LED Controller Avalon Bus

9. Proposed system architectur e January 21, 2011GT20109 Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module : Data flow : Control signal : Data flow : Control signal LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU Slave CPU Raw ECG Data ROM External Memory External Memory Shared Memory Shared Memory

10. Results of logic synthesis January 21, 2011GT201010 System model Logic utilizationBlock memory bitsFmax (MHz) Power (mW) Combinational ALUTs Memory ALUTs Dedicated Logic registers Total 1-lead9,7761611,69615%1,223,688(22%)96.43621.53 2-lead17,3253221,39327%2,351,368(42%)132.49627.23 3-lead24,8634831,08838%2,954,504(52%)119.42632.41 Scale of systems become larger in proportion to the number of leads

11. Execution time January 21, 2011GT201011

12. January 21, 201112GT2010 Decrease 38% Execution time

13. January 21, 201113GT2010 Decrease 50% Execution time

14. Conclusion January 21, 2011GT201014 Parallel processing of the ECG signals from 2-lead and 3-lead. Execution time in 2-lead system was about 38% less than in 1-lead system Execution time in 3-lead system was about 50% less than in 1-lead system It was difficult to build 4 or more leads system

15. Future work Optimization of PPD algorithm Improvement of the performance of hardware January 21, 2011GT201015

16. January 21, 2011GT201016 Thank you for listening.

17. My research and goal Study of SW and HW architecture of single lead SoC Propose, design and evaluation of a new multi-core system for multi-lead processing January 21, 2011GT201017

18. January 21, 2011GT201018

19. Proposed system architectur e January 21, 2011GT201019 Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module : Data flow : Control signal : Data flow : Control signal LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU Slave CPU Raw ECG Data ROM External Memory External Memory Shared Memory Shared Memory