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Erik Jonsson School of Engineering & Computer Science High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments Yuan Zhou.

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Presentation on theme: "Erik Jonsson School of Engineering & Computer Science High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments Yuan Zhou."— Presentation transcript:

1 Erik Jonsson School of Engineering & Computer Science High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments Yuan Zhou 1, Hongda Xu 1, Yun Chiu 1 Datao Gong 2, Tiankuan Liu 2, Jingbo Ye 2 1 University of Texas at Dallas, Richardson, TX, USA 2 Southern Methodist University, Dallas, TX, USA

2 TWEPP 2014- 2 -2014-09-24 Outline Introduction Recent Advances in SAR ADCs Our Recent 12-bit SAR ADC Works  45-MS/s SAR Prototype (0.13μm, 2010)  160-MS/s SAR Prototype (40nm, 2014) Total Ionization Dose (TID) Results (40nm) Summary

3 TWEPP 2014- 3 -2014-09-24 Outline Introduction Recent Advances in SAR ADCs Our Recent 12-bit SAR ADC Works  45-MS/s SAR Prototype (0.13μm, 2010)  160-MS/s SAR Prototype (40nm, 2014) Total Ionization Dose (TID) Results (40nm) Summary

4 TWEPP 2014- 4 -2014-09-24 ADC in Phase-II LAr Readout FEB High resolution: 12-14 bits High speed: 40-80 MS/s Low power, low area Radiation tolerant Detector Output Signal Analog Shaper Preamp Potential Phase-II Upgrade FEB (On detector) MUX & Serializer MUX & Serializer ADC Optical Links To Back-end

5 TWEPP 2014- 5 -2014-09-24 Architecture Choice: SAR vs. Pipeline Pipelined ADC: High-gain residue amplifier hard to scale w/ process SAR ADC: low-power, low-area is a strong candidate for Phase-II SAR Pipeline

6 TWEPP 2014- 6 -2014-09-24 Outline Introduction Recent Advances in SAR ADCs Our Recent 12-bit SAR ADC Works  45-MS/s SAR Prototype (0.13μm, 2010)  160-MS/s SAR Prototype (40nm, 2014) Total Ionization Dose (TID) Results (40nm) Summary

7 TWEPP 2014- 7 -2014-09-24 ISSCC & VLSI data 100mW 1W 10mW1mW 100μW10μW Efficiency = Power/(2∙BW∙3 ENOB ) Performance = 2∙BW∙3 ENOB 10W Pipeline ADC SAR ADC Best design SAR and Pipelined ADCs (<2014) Constant-Power Hyperbola Power Constant Performance X∙Y = Power Performance Efficiency Constant Efficiency

8 TWEPP 2014- 8 -2014-09-24 Outline Introduction Recent Advances in SAR ADCs Our Recent 12-bit SAR ADC Works  45-MS/s SAR Prototype (0.13μm, 2010)  160-MS/s SAR Prototype (40nm, 2014) Total Ionization Dose (TID) Results (40nm) Summary

9 TWEPP 2014- 9 -2014-09-24 12-bit, 45-MS/s, 0.13-μm CMOS ADC Sub-binary DACODC R EDUNDANCY CAL

10 TWEPP 2014- 10 -2014-09-24 Sub-Binary DAC and Redundancy Super-binaryBinarySub-binary Built-in redundancy helps combat dynamic conversion errors (DAC mismatch, comparator, DAC settling, even SEU) Redundancy is also needed for digital claibration

11 TWEPP 2014- 11 -2014-09-24 ODC is implemented in DAC w/ a small cap Digital Post-Processing Offset Double Conversion (ODC)

12 TWEPP 2014- 12 -2014-09-24 How to determine Bit Weights? Is the transfer curve shift-invariant?

13 TWEPP 2014- 13 -2014-09-24 How to determine Bit Weights? Is the transfer curve shift-invariant?

14 TWEPP 2014- 14 -2014-09-24 How to determine Bit Weights? Is the transfer curve shift-invariant?

15 TWEPP 2014- 15 -2014-09-24 Shift-invariant ONLY when the transfer curve is completely linear! Non-constant difference b/t D + and D − reveals bit weight information How to determine Bit Weights?

16 TWEPP 2014- 16 -2014-09-24 12-bit, 45-MS/s, 0.13-μm CMOS ADC Sub-binary DACODC Die size: 0.06 mm 2 12 b, 45 MS/s in FG mode 3-mW power (36.3 fJ/step) Most read JSSC article Nov. 2011

17 TWEPP 2014- 17 -2014-09-24 Measured ADC Spectra (BG Mode) After Cal. Before Cal. SNDR = 60.2dB SFDR = 66.4dB THD = -61.7dB SNDR = 70.7dB SFDR = 94.6dB THD = -89.1dB

18 TWEPP 2014- 18 -2014-09-24 Comparison with 12-bit ADCs 0.06 mm 2 46 fJ/step @ 22.5 MS/s 31 fJ/step @ 45 MS/s Total Power: 3.0 mW (@ time of publication)

19 TWEPP 2014- 19 -2014-09-24 Outline Introduction Recent Advances in SAR ADCs Our Recent 12-bit SAR ADC Works  45-MS/s SAR Prototype (0.13μm, 2010)  160-MS/s SAR Prototype (40nm, 2014) Total Ionization Dose (TID) Results (40nm) Summary

20 TWEPP 2014- 20 -2014-09-24 (5b + 8b) synchronous two-step pipelined SAR architecture First-stage capacitor weights identified w/ opportunistic DAC dither 12-bit, 160-MS/s, 40-nm CMOS ADC

21 TWEPP 2014- 21 -2014-09-24 Smaller output swing for residue amplifier Compensated by 2 nd stage SAR ADC ― Increased resolution (7 bit  8 bit) ― Scaled reference voltage (V ref  0.5V ref ) 1-bit redundancy tolerates offset Subranging, Swing, and Linearity

22 TWEPP 2014- 22 -2014-09-24 Two-stage amplifier provides ~ 30-dB gain Gain error is lumped into bit weights and calibrated Simple Residue Amplifier

23 TWEPP 2014- 23 -2014-09-24 Reference voltage is effectively halved Minimal loading determined by kT/C noise Second-Stage SAR ADC

24 TWEPP 2014- 24 -2014-09-24 Die Photo 40-nm digital CMOS process (die size = 0.042 mm 2 ) Integrator + DAC MDAC1 MDAC2 MDAC3 MDAC4 Sub- ADC1 Sub- ADC2 Sub- ADC3 Sub- ADC4 Sub- ADC5 Clock & PN Gen. 300μm 139μm

25 TWEPP 2014- 25 -2014-09-24 Measured ADC Dynamic Performance fs = 160MHz after cal.fin = 25MHz after cal. f Nyquist =80MHzf s =160MHz fin [MHz] fs [MHz]

26 TWEPP 2014- 26 -2014-09-24 Analog 1.1V 2.8mW (53.6%) Total power is ~ 5 mW at 160-MS/s operation Power Breakdown (VLSI’14 Version)

27 TWEPP 2014- 27 -2014-09-24 ISSCC & VLSI data 100mW 1W 10mW1mW100μW10μW Efficiency Performance 10W Best design 12b,160MS/s 5mW ADC PE Chart Revisited

28 TWEPP 2014- 28 -2014-09-24 Outline Introduction Recent Advances in SAR ADCs Our Recent 12-bit SAR ADC Works  45-MS/s SAR Prototype (0.13μm, 2010)  160-MS/s SAR Prototype (40nm, 2014) Total Ionization Dose (TID) Results (40nm) Summary

29 TWEPP 2014- 29 -2014-09-24 TID Test of 40-nm CMOS SAR ADC DUT under X-ray radiation when powered up w/ clock input. ADC performance (e.g., SNDR, SFDR, power, etc.) measured after irradiation is complete.

30 TWEPP 2014- 30 -2014-09-24 Measured SNDR and SFDR @ 80 MS/s

31 TWEPP 2014- 31 -2014-09-24 Measured SNDR and SFDR @ 160 MS/s

32 TWEPP 2014- 32 -2014-09-24 Annealing (f s = 80 MS/s)

33 TWEPP 2014- 33 -2014-09-24 Annealing (f s = 160 MS/s)

34 TWEPP 2014- 34 -2014-09-24 Measured ADC Power

35 TWEPP 2014- 35 -2014-09-24 Outline Introduction Recent Advances in SAR ADCs Our Recent 12-bit SAR ADC Works  45-MS/s SAR Prototype (0.13μm, 2010)  160-MS/s SAR Prototype (40nm, 2014) Total Ionization Dose (TID) Results (40nm) Summary

36 TWEPP 2014- 36 -2014-09-24 Summary Thank you for your attendance! High-resolution and high-speed SAR ADC is a strong candidate to meet the stringent requirements in HEP experiments The preliminary irradiation test (TID) results further highlight the feasibility of SAR ADC in deeply scaled CMOS processes for HEP applications Low power and small die size of SAR present great potentials for spatial redundancy technique to be employed in single-event upset (SEU) treatment

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