1. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.1 Operating System Concepts Operating Systems Lecture 33 Paging Read Ch. 9.4

2. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.2 Operating System Concepts Paging Paging allows the physical address space of a process to be non-contiguous. Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes). Divide logical memory into blocks of same size called pages. Each address generated by the CPU consists of a page number, p, and an offset, d.  Page number: Index to a page table that contains the base address of the corresponding frame in physical memory.  Page offset: Combined with the base address to define the physical memory address that is sent to the memory unit.

3. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.3 Operating System Concepts Address Translation Architecture

4. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.4 Operating System Concepts Paging Example

5. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.5 Operating System Concepts Storing of Addresses Suppose the size of physical address space = 2 m Suppose the page size = 2 n What is the total number of pages? Allocate m bits to specify logical addresses. First m - n bits of the address specify the page number. The n lower order bits indicate the offset.

6. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.6 Operating System Concepts Paging Example Page size = 4 bytes Physical memory = 32 bytes Number of pages = ? Where do the following map? Logical 0: Page 0, offset 0: Logical 3: Page 0, offset 3: Logical 4: Logical 13:

7. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.7 Operating System Concepts Paging and Fragmentation Don't have external fragmentation with paging.  Any free frame can be allocated to a process that needs it. May have internal fragmentation with paging.  Frames are allocated as units. Last frame may not be completely full.

8. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.8 Operating System Concepts Allocation of Frames The O.S. keeps track of which frames are allocated and which are free in a frame table. If a process requests n frames, there must be n frames available to satisfy the request. If so, they are allocated to the process. As each frame is allocated to each page, the frame number is put in the page table for that process. Note: The user views memory as contiguous space. The program is actually scattered throughout physical memory.

9. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.9 Operating System Concepts Free Frames Before allocation After allocation

10. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.10 Operating System Concepts Implementation of Page Table Simplest implementation: Page table stored in dedicated registers in the CPU. The registers use high speed logic. The CPU dispatcher re-loads these registers when switching processes. (Each process has its own page table). Example: DEC PDP-11  Address size = 16 bitsNumber of addresses = ?  Page size = 8 KB (8192) = 2 13 Number of bits = ?  Number of pages = ?  # of entries in page table = number of pages = ? This method is only useful when the page table is small (< 256 entries). Most contemporary computers have much larger page tables (10 6 entries) so this method will not work well.

11. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.11 Operating System Concepts Storing Page Table in Main Memory For large page tables, the page table is kept in main memory. Page-table base register (PTBR) points to the page table. When changing processes, only need to change 1 register to change page tables. This reduces the context switch time. Page-table length register (PTLR) indicates size of the page table. Drawback: In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.

12. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.12 Operating System Concepts Translation Look-Aside Buffer (TLB) The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)  This kind of memory is expensive, so it is generally small (64 - 1024 entries). In each memory access, the TLB is searched first to locate the page number.  If the page is found (a hit) the associated frame is used to access the data in memory.  If the page is not found (a miss), the page number is looked up in the page table in main memory. The page number and associated frame is added to the TLB.

13. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.13 Operating System Concepts TLB: Associative Memory Associative memory – parallel search Address translation (Page #, Frame #)  If page# is in associative register, get frame # out.  Otherwise get frame # from page table in memory Page #Frame #

14. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.14 Operating System Concepts Paging Hardware With TLB

15. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.15 Operating System Concepts Effective Access Time (EAT) Effective access time (EAT) is the average time needed to access memory. Hit Ratio: The percentage of times that a particular page number is found in the TLB. Effective access time can be calculated based on:  The time it takes to access main memory  The time it takes to access the TLB  The hit ratio for the TLB Example  Time to access main memory = 100ns  Time to access TLB = 20 ns  Hit ratio = 0.8 (80%)  If page is found in TLB, total access time = ?  If page is not found in TLB, total access time = ?  Effective access time = ?

16. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.16 Operating System Concepts General Formula for EAT Hit ratio =  Main Memory access time = m Associative Lookup (TLB access) =  EAT = (m +  )  + (2m +  ) (1 -  ) = 2m - m  + 

17. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.17 Operating System Concepts Memory Protection Memory protection implemented by associating protection bit with each frame.  Bits signal if a frame is read only, read-write, execute only or a combination. Valid-invalid bit attached to each entry in the page table:  “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page.  “invalid” indicates that the page is not in the process’ logical address space. Example:  System has 14 bit address space (0 - 16383)  Program uses addresses 0 - 10468  Page size = 2 KB (2048 = 2 11 )  # of pages = ?  6 pages needed by program (5 pages = 5*2048 = 10240Bytes)  Pages 0 - 5 have valid/invalid bit set to valid  Other pages have bit set to invalid.

18. Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, 2005 7.18 Operating System Concepts Valid (v) or Invalid (i) Bit In A Page Table