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EE141 © Digital Integrated Circuits 2nd Introduction 1 Digital Integrated Circuits A Design Perspective Introduction Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic July 30, 2002
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EE141 © Digital Integrated Circuits 2nd Introduction 2 What is this book all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
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EE141 © Digital Integrated Circuits 2nd Introduction 3 Digital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures
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EE141 © Digital Integrated Circuits 2nd Introduction 4 Introduction Why is designing digital ICs different today than it was before? Will it change in future?
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EE141 © Digital Integrated Circuits 2nd Introduction 5 The First Computer
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EE141 © Digital Integrated Circuits 2nd Introduction 6 ENIAC - The first electronic computer (1946)
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EE141 © Digital Integrated Circuits 2nd Introduction 7 The Transistor Revolution First transistor Bell Labs, 1948
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EE141 © Digital Integrated Circuits 2nd Introduction 8 The First Integrated Circuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966
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EE141 © Digital Integrated Circuits 2nd Introduction 9 Intel 4004 Micro-Processor Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation
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EE141 © Digital Integrated Circuits 2nd Introduction 10 Intel Pentium (IV) microprocessor
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EE141 © Digital Integrated Circuits 2nd Introduction 11 Moore’s Law lIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. lHe made a prediction that semiconductor technology will double its effectiveness every 18 months
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EE141 © Digital Integrated Circuits 2nd Introduction 12 Moore’s Law Electronics, April 19, 1965.
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EE141 © Digital Integrated Circuits 2nd Introduction 13 Evolution in Complexity
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EE141 © Digital Integrated Circuits 2nd Introduction 14 Transistor Counts 1,000,000 100,000 10,000 1,000 10 100 1 19751980198519901995200020052010 8086 80286 i386 i486 Pentium ® Pentium ® Pro K 1 Billion Transistors Source: Intel Projected Pentium ® II Pentium ® III Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 15 Moore’s law in Microprocessors 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 19701980199020002010 Year Transistors (MT) 2X growth in 1.96 years! Transistors on Lead Microprocessors double every 2 years Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 16 Die Size Growth 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 19701980199020002010 Year Die size (mm) ~7% growth per year ~2X growth in 10 years Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 17 Frequency P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 1000 10000 19701980199020002010 Year Frequency (Mhz) Lead Microprocessors frequency doubles every 2 years Doubles every 2 years Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 18 Power Dissipation P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 197119741978198519922000 Year Power (Watts) Lead Microprocessors power continues to increase Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 19 Power will be a major problem 5KW 18KW 1.5KW 500W 4004 8008 8080 8085 8086 286 386 486 Pentium® proc 0.1 1 10 100 1000 10000 100000 19711974197819851992200020042008 Year Power (Watts) Power delivery and dissipation will be prohibitive Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 20 Power density 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 21 Not Only Microprocessors Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU ) Power Management Small Signal RF Power RF (data from Texas Instruments) Cell Phone
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EE141 © Digital Integrated Circuits 2nd Introduction 22 Challenges in Digital Design “Microscopic Problems” Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different “Macroscopic Issues” Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. …and There’s a Lot of Them! DSM 1/DSM ?
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EE141 © Digital Integrated Circuits 2nd Introduction 23 Productivity Trends 1 10 100 1,000 10,000 100,000 1,000,000 10,000,000 200319811983198519871989199119931995199719992001200520072009 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic Transistor per Chip (M) 0.01 0.1 1 10 100 1,000 10,000 100,000 Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Complexity Courtesy, ITRS Roadmap
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EE141 © Digital Integrated Circuits 2nd Introduction 24 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstraction
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EE141 © Digital Integrated Circuits 2nd Introduction 25 Design Abstraction Levels n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM
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EE141 © Digital Integrated Circuits 2nd Introduction 26 Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function
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EE141 © Digital Integrated Circuits 2nd Introduction 27 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area
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EE141 © Digital Integrated Circuits 2nd Introduction 28 NRE Cost is Increasing
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EE141 © Digital Integrated Circuits 2nd Introduction 29 Die Cost Single die Wafer From http://www.amd.com Going up to 12” (30cm)
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EE141 © Digital Integrated Circuits 2nd Introduction 30 Cost per Transistor 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 1982198519881991 1994 199720002003200620092012 cost: ¢-per-transistor Fabrication capital cost per transistor (Moore’s law)
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EE141 © Digital Integrated Circuits 2nd Introduction 31 Yield
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EE141 © Digital Integrated Circuits 2nd Introduction 32 Defects is approximately 3
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EE141 © Digital Integrated Circuits 2nd Introduction 33 Some Examples (1994) ChipMetal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer YieldDie cost 386DX 20.90$9001.04336071%$4 486 DX2 30.80$12001.08118154%$12 Power PC 601 40.80$17001.312111528%$53 HP PA 7100 30.80$13001.01966627%$73 DEC Alpha 30.70$15001.22345319%$149 Super Sparc 30.70$17001.62564813%$272 Pentium 30.80$15001.5296409%$417
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EE141 © Digital Integrated Circuits 2nd Introduction 34 Reliability― Noise in Digital Integrated Circuits i(t) Inductive coupling Capacitive couplingPower and ground noise v (t) V DD
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EE141 © Digital Integrated Circuits 2nd Introduction 35 DC Operation Voltage Transfer Characteristic V(x) V(y) V OH V OL V M V OH V OL f V(y)=V(x) Switching Threshold Nominal Voltage Levels VOH = f(VOL) VOL = f(VOH) VM = f(VM)
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EE141 © Digital Integrated Circuits 2nd Introduction 36 Mapping between analog and digital signals V IL V IH V in Slope = -1 V OL V OH V out “0” V OL V IL V IH V OH Undefined Region “1”
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EE141 © Digital Integrated Circuits 2nd Introduction 37 Definition of Noise Margins Noise margin high Noise margin low V IH V IL Undefined Region "1" "0" V OH V OL NM H L Gate Output Gate Input
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EE141 © Digital Integrated Circuits 2nd Introduction 38 Fan-in and Fan-out N Fan-out N Fan-in M M
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EE141 © Digital Integrated Circuits 2nd Introduction 39 The Ideal Gate R i = R o = 0 Fanout = NM H = NM L = V DD /2 g = V in V out
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EE141 © Digital Integrated Circuits 2nd Introduction 40 Delay Definitions
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EE141 © Digital Integrated Circuits 2nd Introduction 41 Ring Oscillator T = 2 t p N
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EE141 © Digital Integrated Circuits 2nd Introduction 42 A First-Order RC Network v out v in C R t p = ln (2) = 0.69 RC Important model – matches delay of inverter
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EE141 © Digital Integrated Circuits 2nd Introduction 43 Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power:
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EE141 © Digital Integrated Circuits 2nd Introduction 44 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p
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EE141 © Digital Integrated Circuits 2nd Introduction 45 Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this book Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation
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