1. Muon Trigger Performance Run12 PP510GeV Sanghwa Park (SNU/RIKEN)

2. PHENIX Run12 510GeV 5 weeks The first PHYSICS run: March 18 th The last PHYSICS run: April 18 th 2012/12012/22012/32012/4 PP200GeVPP510GeV

3. MuTRG-FEE(Front-End-Electronics) – Momentum sensitive trigger & fast readout electronics RPC (Resistive plate chamber) – Good timing resolution Hadron absorber – Reject hadron(K, π) to muon decay Trigger Upgrade History 2008200920102011 MuTRG- FEE (North arm) MuTRG-FEE (South arm) RPC3 (North) RPC3 (South) Hadron Absorber RPC1

4. W Trigger System MuTRG ADTX MuTRG MRG Level 1 Trigger Board MuTr FEE Resistive Plate Counter (RPC) (Φ segmented) B 2 planes 5% 95% Trigger Interaction Region Rack Room Optical 1.2Gbps Amp/Discri. Transmit Data Merge MuTRG RPC FEE Trigger events with straight track (e.g.  strip <= 1) RPC / MuTRG data are also recorded on disk.

5. Run12 MuTRG-EFF Parameters Parameters Threshold 97% efficiency threshold -> 95% efficiency threshold (changed during run period for higher rejection power) DiscriminatorLED Gap Logic Station1Station2 and 3 AND2OR LL1 width3 BCLK

6. MuTRG-FEE Timing Optimization Limitation of broad timing resolution: ~2-3BCLK Extend timing window to 3BCLK(maximum) BCLK Binning in ADTX Offset BCLK Entry (Normalized) Motivation: Find best timing offset which maximize entries in finite timing window 42.9 nsec 88.3 nsec 6

7. Inserted delay fiber cable to MuTrig-FEE GTM line, remaining GTM setting for MuTr untouched. Couldn’t adjust timing MuTrigLL1 timing for south arm with fiber delay Insert fiber cable only for north arm, 4m (20 nsec) MuTRG-FEE Timing Optimization y-axis: (3BCLK/Total entries) of st1 * st2 * st3

8. New FPGA code uploaded New FPGA code for MuTRG-MRG boards was developed by Katsuro Nakamura. Important changes: - detailed error detection - use independent clock signal for readout - 10 nsec faster MRG->LL1 output timing - can give delay to LL1 output timing board by board New FPGA success story - find suspicious ADTX board id which caused frequent error - solved LL1 efficieny drop problem caused by the above error

9. W Trigger Rejection Power Needed to set prescale when luminosity is high We had kept two w trigger during entire pp510 GeV run period

10. W Trigger Check Run11 w trigger: SG1xMUIDxBBC(noVtx) Run12 w trigger: SG1xRPC3xBBC(noVtx)

11. Muon yield Cut Parameters DG0 < 5.0 DDG0 < 1.0 Chi2 < 8.0 DCA_r <3.0 DCA_z < 7.0 DG4 < 4.8 MUID lastGap == 4 1.5 <eta < 2.2 for north, -2.2 < eta < -1.5 for south *RpcDCA > 0 was not applied for this result. SG1xMUIDxBBC SG1xRPC3xBBC SG1xMUIDxBBC SG1xRPC3xBBC South North (* not scaled) Big difference between two trigger, especially in low pT region

12. 12 Muon yield : SG1xRPC3 south : SG1xMUID south : SG1xRPC3 north : SG1xMUID north Run set2

13. 13 South SG1xRPC3xBBC North SG1xRPC3xBBC South SG1xMUIDxBBC North SG1xMUIDxBBC RpcDCA distribution (all pT region) Same trigger, South and North comparison In low pT region, SG1xMUID north yield is larger tham south. It seems it corresponds to this region. In other hands, in high pT region, SG1xMUID south yield is larger than north, and this difference is showed in small RpcDCA region.

14. Closer look at high pT > 5 GeV/c region… RpcDCA [cm] SG1xMUIDxBBC SG1xRPC3xBBC South SG1xMUIDxBBC SG1xRPC3xBBC North Basically used same cuts with muon yield plots. Additional cut: pT > 5 GeV region only. 14

15. 15 Used same cut parameters as slide4, but required one more cut additionally. If we require RpcDCA > 0, the difference between SG1xMUIDxBBC south and north is drastically reduced! RpcDCA cut: before/after Red: before RpcDCA>0 cut Black: after RpcDCA>0 cut Red: before RpcDCA>0 cut Black: after RpcDCA>0 cut SG1xRPC3xBBC south Orange: before RpcDCA>0 cut Black: after RpcDCA>0 cut Orange: before RpcDCA>0 cut Black: after RpcDCA>0 cut SG1xMUIDxBBC south

16. RpcDCA cut: before/after 16 Used same cut parameters as slide4, but required one more cut additionally. If we require RpcDCA > 0, the difference between SG1xMUIDxBBC south and north is drastically reduced! Cyan: before RpcDCA>0 cut Black: after RpcDCA>0 cut Cyan: before RpcDCA>0 cut Black: after RpcDCA>0 cut SG1xMUIDxBBC north Blue: before RpcDCA>0 cut Black: after RpcDCA>0 cut Blue: before RpcDCA>0 cut Black: after RpcDCA>0 cut SG1xRPC3xBBC north

17. Rpctime distribution (all pT region) SG1xMUIDxBBC SG1xRPC3xBBC North SG1xMUIDxBBC SG1xRPC3xBBC South SG1xMUIDxBBC SG1xRPC3xBBC South SG1xMUIDxBBC SG1xRPC3xBBC North 17

18. Closer look at high pT > 5 GeV/c region… SG1xMUIDxBBC SG1xRPC3xBBC South SG1xMUIDxBBC SG1xRPC3xBBC North Basically used same cuts with muon yield plots. Additional cut: pT > 5 GeV region only. RpcDCA >0, for rough association with MuTR hit (No difference, between with RpcDCA>0 cut and without RpcDCA>0 cut) 18

19. In high pT region, two triggers are getting consistent. RpcDCA >0 cut makes drastic difference. Based on study, we set prescale to SG1xMUIDxBBC trigger in high luminosity beam. Working on this for more deeper study: - luminosity correction

20. MuTrig LL1 Efficiency South octant3 South octant5 MuTrig LL1 was overall stable, and in good state. BUT, south octant5 was not stable, and the efficiency was low. -> couldn’t figure out the reason yet. SG1xBBCnoVtx trigger

21. MuTrig LL1 Efficiency Thanks to the great effort of LL1 experts, MuTrig LL1 timing adjustment was successfully done. SG1xRPC3xBBC trigger was in bad state for one day. South octant3 SG1xRPC3xBBCnoVtx trigger

22. MuTRG-FEE Error Monitoring South North Oct8,1 Oct2,3 Oct4,5 Oct6,7 No error Known errors. To be fixed during shutdown 22 ADTX boards have been in good operation status except for known bad boards.

23. Summary We had taken data over 30 pb-1 this year. Several update: -Fiber insertion to MuTrig-FEE for increasing efficnecy -New FPGA code was successfully uploaded - Figured out bad ADTX boards, and need replace during shut down period New w trigger was introduced: SG1xRPC3xBBC MuTrig LL1: need to figure out south octant5 low efficieny Thank you for great effort of all

24. Backup

25. Integr. Luminosity

26. Run11 vs Run12 GTM scan result South St1 South St2 South St3North St3 North St2 North St1 Delay time [nsec] 26Spin PWG meeting February 22, 2012

27. Final Result Optimized delay: 14.2 SouthNorth Optimized delay: 24.3 y-axis= st1 * st2 * st3 27Spin PWG meeting February 22, 2012

28. MuTRG operation in 2011 Parameters Average Threshold25 mV DiscriminatorLED Gap Logic Station1Station2 and 3 AND2OR LL1 width3 BCLK Efficiency at Plateau 92% (South arm) 87% (North arm)

30. LL1 Trigger efficiency LL1 Trigger efficiency? RPC St3 St2 St1 MuTRG-ADTX boards MuTRG-MRG hit pattern copy LL1 Trigger DCMIF DCM Trigger Real trigger fire Expected trigger fire Inequality? LL1 Efficiency

31. MuTrig LL1 Effiency (SG1xBBC north)

32. MuTrig LL1 Effiency (SG1xBBC south) South octant5 Xaxis: Run Number, Yaxis: Efficiency

33. MuTrig LL1 Effiency (SG1xRPC3 north)

34. MuTrig LL1 Effiency (SG1xRPC3 south)