1. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 1 email: deptuch@ieee.org VIPIC – subreticule J Fermilab ASIC Group, USA Grzegorz Deptuch, Marcel Trimpl, Raymond Yarema AGH UST, POLAND Pawel Grybos, Robert Szczygiel, PhD students: Maciej Kachel, Piotr Kmon  OUTLINE: 1) Application, 2) Specification, 3) Architecture of VIPIC 4) Mounting options on the detector, 5) Details of circuitry a) Analog, b) Digital, 6) Details of layouts 7) Preparation of tests, 8) Conclusions.

2. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 2 Application Suggestion from Peter Siddons; BNL XPCS is a novel technique that studies the dynamics of various equilibrium and non-equilibrium processes occurring in condensed matter systems (e.g. gels, colloids, liquid crystals, bio-materials, membranes, metals, oxides, magnets, etc.) XPCS is based on the generation of a speckle pattern by the scattering of coherent X-rays from a material where spatial nonhomogeneities are present. If the state of disorder of the system changes with time, the speckle pattern will change. Thus by studying the time dependence of the scattered intensity, one can study the dynamics of the materials both in or out of thermodynamic equilibrium (e.g. diffusion constants, magnetic domain relaxation times, phase transformations) Advantages –Observe smaller features sizes –Can be used to observe charge, spin, chemical and atomic structure behavior. –Works with non-transparent materials Speckle pattern XPCS – X-ray Photon Correlation Spectroscopy

3. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 3 Application target is to output time stamped information  t=10  s for long exposure times; very low occupancy < 10 ph/mm 2 /10  s final results are not actual images but mathematical representation of autocorrelation series computed per spatial position

4. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 4 –Design optimized for 8 keV X-ray photons (amplifier range up to 3 × 8 keV with Si detector) –64 × 64 array of 80  m 2 pixels 5120 × 5120  m 2 active surface –Die size 5.5 × 6.3 mm 2 –12-bit DAC for adjustments / pixel (12 × 64 × 64 bit long shift register, with 12-bit latch register/pixel, global analog adjustment of the DAC range) - 7 bit threshold setting / pixel - 3 bit adjustment of feedback resistance in the first stage / pixel - 1 bit selection between single ended and differential architecture / pixel - 1 bit injecting test pulse enable (calibration block with injection capacitance / pixel) –‘Set’ and ‘Kill’ bits / pixel (two separate shift registers 64 × 64 long, priority of ‘kill’ over ‘set’, ‘kill’ disables reception of hits in digital section – analog stage and discriminator are active) –Shaping time  p =250 ns, power consumption ~25  W / analog pixel –Noise <150 e - ENC –Dead timeless operation (operation divided into time slots: hits arriving in time  t n-1 are read out in  t n while simultaneously new hits are being acquired in time  t n ) –Sparsified data readout based on priority encoder circuit (binary tree) with automatic binary-coded generation of hit pixel addresses –Hit pixel address readout only (no energy information available) –No trigger acceptance, Design specification

5. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 5 Design specification –Two modes of operation: 1) timed readout of hits acquired at low occupancy (address and hit count) 2) imaging (two 5 bit-long counters / pixel accumulates hits occuring in each time slot, readout uses sparsification mechanism but no readout of addresses t read = (f clk ) -1 × 16 bits × 4 × 64 – can be <100  s) –64 × 64 matrix divided in 16 submatrices of 4 × 64 pixels –16 parallel LVDS output lines, adjustable currents 1 mA, 2 mA, 4 mA, 8 mA any combination possible (max 15 mA), higher value I-V conversion resistors can be used or in case of problems –Analog and digital functions fully separated between tiers (tier 1 and tier 2) analog = 280 transistors digital = 1400 transistors –Aproach to demonstate 4 side buttable X-ray detector. Two options of bonding to the detector and placement of I/Os, power supply and bias pads: 1) fanout on the detector; detector attached on the back of analog tier, pads bonded to the traces on the detector and redistributed outside of the chip contour for bonding 2) one side bonded to the detector - opposite side bonded to the PCB board all I/Os, power and bias connection transfered to the digital tier - 215 bump bonding pads in staggered layout in 450um pitch (320 if it was square)

6. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 6  160 ns / hit pixel in sparsified mode  50×10 3 frame/s in imaging mode (5 bit counting) VIPIC = Vertically integrated Photon Imaging Chip VIPIC = Vertically integrated Photon Imaging Chip Architecture of VIPIC

7. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 7  OPTION 1 – LESS AGGRESSIVE MOUNTING  Access to signals, power supplies and biases, etc. : - fanout/routing on the detector, pads created on the detector, wire bonding to mount in the system Mounting options on the detector

8. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 8 Mounting options on the detector - both-side bonding (thinning, exposing TSV, deposition of bonding pads) - both-side bonding (thinning, exposing TSV, deposition of bonding pads)  OPTION 2 – MORE AGGRESSIVE MOUNTING for 4-side buttable sensor arrays and improved power distribution

9. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 9 Mounting options on the detector  VIPIC – NOW: pads are duplicated  VIPIC – FUTURE: cut away dead silicon, no classical padring (tedious layout work)

10. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 10 Mounting options on the detector  VIPIC – NOW: all pads are rerouted from ‘front – side’ to ‘back-side’  Pads are uniformingly distributed over whole ‘back side’ This is vdda pixelThis is vddd pixel

11. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 11 Mounting options on the detector  View of pads on back-side of VIPIC Multiple pads for the the same nodes grouped together for easier routing of power supply on PCB

12. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 12 Mounting options on the detector  View of pads on back-side and pixel groups of VIPIC Not all pads distributed over area occupied by pixels (to be improved in future) 16 groups read out simultaneously

13. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 13  View of pads on front-side of VIPIC Mounting options on the detector Pads for power supplies, biases, digitial control, etc. 64 × 64 pads for detector diodes 16 pairs of LVDS outputs

14. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 14 Details of circuitry - Analog EnableCal_B, Diff/Single, CSAResFeed, ThreshTrim

15. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 15 Cf = 8 fF Rf =tuned from tens to hundreds of MΩ Input transistor PMOS W/L = 20µm/0.2um, Id=5 µA CSAout SHAPER out Qin = 2200 el (8keV in Si) CSAout= 34 mV (added Cinteg) SHAPER out= 113 mV (Tp = 220ns) CSA+feedback stability Cdet = 100fF, Cf=8fF PhMag=88 deg

16. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 16 CSA differential/ single ended mode switched using internal register TEST- rejection of common input pulses IN: Qin=2200 el, f = 200 kHz Common input pulses (applied to IN & INR: Qin=2200 el, f=200 kHz, delay time 2.5us) Differential mode: ENC = 94 el rms (Cdet=100f) PWR = 28 uW/pixel Single-ended mode: ENC = 80 el rms (Cdet=100f) PWR = 22 uW/pixel Remark: in each case the tests were performed for Cdet=0 & Cdet=100fF (detector capacitance adds some asymmetry between IN and INR)

17. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 17 Linearity CSA\shaper output linearity Qin=1100 el - 6600el Step: 1100 el. Discriminator threshold vs. X-ray energy

18. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 18 Shaper: Pule-ups for high rate of input pulses Shaper output Qin=2200 el (fin=200kHz) Baseline shift at discriminator inputs =33 mV

19. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 19 Details of circuitry - Digital Part of shift register; Pixel can be permanently reset (no hits) or set (always hit) During  t n hits from  t n+1 go to ‘waiting room’ With rising edge of TS_Clk hits are shifted to ‘service room’ where they are ready for readout RStrobe removes hit from read-out queue Acknowledge from priority encoder Prevents counting hits twice (requests dis_in ‘LOW’ after rising edge of TS_Clk ) Ambiguous situation when discriminator is high at the boundary of adjacent time slices

20. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 20 Details of circuitry - Digital Counters are used with alternated enable signals: for counting / for readout To minimize switching activity, enable signals are not alternated with time stamping clock but only when new hit has occured in new time slot (if no hit was in ‘waiting room’ no swapping of counters)

21. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 21 Details of circuitry - Digital Based on: P.Fischer, Nucl. Instr. and Methods in Physics Research A, 461, 2001, pp. 499-504 Logic (with tri-state capability) allowing generation of binary addresses on the address bus Equivalent of giant OR Priority encoder Pulled down when no hit at all (generates address 0000 hex ) tedious semi- automatic / full custom layout; logic ditributed among all pixels in a group; last two leaves located outside the matrix

22. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 22 Details of circuitry - Digital Two levels of HIT OR tree and priority encoder Part of binary address generator There is no full symmetry (there are NOR and NAND levels) – two ‘pixels’ were created Address generator are not symmetric either System is complex and layout tedious but results in very powerful sparsification engine

23. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 23 Example of readout sequence 1 hit at address 2; 2 hits at adress 13 Details of circuitry - Digital 010 start new hit marker Programming sequence – simple shist register

24. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 24 Details of circuitry - Digital Programming of VIPIC uses 3 shift registers: set, reset, analog pixel configuration

25. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 25 Content of counter read always first; this enables an imaging mode where NO pixel adresses are read; All pixels must be set permanently Full timing diagram of readout sequence Details of circuitry - Digital why 5 bit counters are not too short: 1  s long pulse (  s =250 ns)  maximum rate of event that be counted is less than 1 MHz, The depth of 5 bit counters is 32  32  s to fill up the counter, 8 bits (3 bits of starting sign overload) × 10 ns (serial clock) × 256 (pixels in the group) = 20.4  s 5 bit long counters  operation maximum counting speed is dictated by the front-end circuitry. continuous readout 1000 hits/1ms/pixel (equivalent of 10bits counter depth) counter address

26. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 26 Details of layouts all metal layers Analog tier (Fermi_VIPIC_J_Left); only back metal

27. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 27 all metal layers Digital tier (Fermi_VIPIC_J_Right); only back metal Details of layouts

28. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 28 Digital part of pixel Analog part of pixel Details of layouts

29. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 29 Preparation of tests PCBs (produced) Test setup (ready) Full chip Verilog simulations (done) NI PXIe-1062QNI PXI-8106 NI-PXI 6562NI-PXI 6259

30. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 30 Preparation of tests 1.Initial current measurements - power supply currents - biasing currents 2.Digital tests - shift registers (set, reset, DAC) - maximum speed and/or min. Vdd. 3.Threshold scan – Rice curves 4.Trimming DAC characteristics 5.Threshold spread correction 6.Tests with internal calibration 7.Tests of different biasing VIPIC initial test list (without detector)

31. 3D-IC Consortium Meeting, Marseilles France, 18-19 March 2010 31 Conclusions  Design accomplished  Waiting for chips to be tested  Work on sensors with BNL – design accomplished – first sensors to be ready soon for verification of bondability at Ziptronix  Preparation of tests – tests of bare chips – tests of chips with detectors (detector mounting with fanout, double sided bonding for 4-side buttable future devices)  Plans on VIPIC 2 with BNL,  Design with increased time stamping precision within longer time window (nanosecond precision within 10  s time window)  Possibility of registering time stamps of a few hits per time window  Chip area 1 × 1 cm 2 (desired)