1. High Multiplicity FVTX Trigger Toru Nagashima, Yomei Fukushima (Rikkyo University) Shoichi Hasegwa (J-Parc) Itaru Nakagawa RIKEN and FVTX Group 1

2. FVTX READOUT AND TRIGGER LOGIC 2

3. FVTX Readout 3 FPGA Slow Control FEM-IB All hits are sent to FEM regardless of trigger request FEM

4. FVTX Trigger Design 4 FPGA Slow Control FEM-IB Raise a “track flag” if track like hit pattern is found. Track flag TRIGGER GL1 If the number of flagged FEMs are more than threshold, then issue a trigger FEM

5. 5 At least one hit in 3 out of 4 stations is required within a half sector ((  =7.5 o ). -> TrackFlag. If there are more than two tracks within a given sector (  =15 o ), the second one won’t be counted. We Request Two Trigger bits (one per arm) for FVTX trigger. AND

6. MB mulitpicity (Pythia) Convert x-axis to Number of FEMs by dividing tracks into phi segments. (Ceaser) Single collision

7. Caveat The # of “semi-tracks” can be counted up to only 24 tracks per event. By taking “AND” between sectors, we can raise it up to 48, but significant efficiency loss is expected. To be studied in offline. 7

8. THE FIRST ATTEMPT TO MEASURE THE TRIGGER EFFICIENCY 8

9. The first attempt to measure trigger efficiency 9 #hits Counter in FPGA Test pin #hits counter >threshold Measurement by Toru Nagashima

10. Cause of inefficiency 10 Measurement by Toru Nagashima

11. Strategy There is only one logical place where we can miss the # of hits. The trigger can be missed only if the hits arrives to FEM after the trigger signal issued. It is tuned by the delay setting. The delay was set long enough for this measurement. Scanning number of hits from one and observe if there is loss of counting. Run the simulation. 11

12. TEST PIN OUT 12

13. FVTX High Multiplicity Trigger (ver.0.3) FEM FEM-IB Test-pin wiring FVTX Hits VME backplane FVTX North West VEM Crate FEM FEM-IB Test-pin wiring FVTX Hits VME backplane FVTX North East VEM Crate Test pin out Test pin in Test pin out TTL - ECL ECL-TTL Differential Flat cable TTL RBIB GL1 Need timing adjustment capability here. 2BCLK Discriminator

14. FEM-IB -> GL1 14 Test-Pin Out Discri-out w/o Veto Veto Discri-out w/ veto Measurement by Yomei Fukushima

15. HARDWARE STATUS 15

16. 16 FEM-IB end FEM end Measurement by Toru Nagashima and Yomei Fukushima

17. All Connectors are delivered. 1 FEM-IB end cable is made. 6~7 FEM end cables are made. 3 FEM-IB end cable to go. 30 FEM end cables to go. Cables to be installed by Itaru and Eric around Nov. 4 th ~. 17

18. BACKUPS 18

19. Reference Charged particle multiplicity dependence of the J/psi yield in p+p collisions at sqrt(s)=510 GeV using run13 data (an1180)

20. 2015

21. FVTX Trigger Design 21 FPGA Slow Control FEM-IB Sum-up hits and flag high multiplicity event in FPGA High multiplicity event flag TRIGGER GL1

22. #hits > threshold 3/4, stations #hits > threshold #SECTOR TRIG > threshold #SECTOR TRIG > threshold AND /OR SECTOR TRIGGER ARM TRIGGE R EAST WEST SECTOR Trigger Algorithm FEM-IB 3/4, stations OR