1. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 1 AGET circuit: Application Information actar

2. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 2 AGET: ASIC Control Asic management (AsAd &/or CoBo) SCA read: READ & CK read SCA write: Write & CK write Slow control: Din, Dout, CK, CS Test: Pulser (Iinj or Vinj) Analog Data Conversion Trigger control: multiplicity & detection AGET 511 cells SCA FILTER tpeak CSA 1 channel x72in 76 to 1 Charge range DAC Discri BUFFER SCA MANAGER SLOW CONTROL TEST hit channel registers Voltage & current supply W CKw R CKr Din CKDoutCs Iinj Vinj Σ 72 discri. Voltage & current sources management (AsAd) Power Supply: 3.3V & gnd d.c voltage: CSA,Filter,Gain2,SCA &dataBuffer d.c current: CSA&dataBuffer

3. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 3 AGET: Voltage & Current sources management Power Supply: AFTER chip: 27 Vdd(3.3V) + 30 Gnd.AFTER chip: 27 Vdd(3.3V) + 30 Gnd. D.C voltage references: CSA,Filter,G2 &SCA: 4 * 2 (left &right).CSA,Filter,G2 &SCA: 4 * 2 (left &right). BUFFER: 2.BUFFER: 2. D.C current references: CSA: 1 * 2 (left &right).CSA: 1 * 2 (left &right). BUFFER: 2.BUFFER: 2. R ext PAD 100nF vdd I ref Inside the chip vdd I Voltage reference Vicm BUFFER (1.45V)

4. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 4 AGET: Slow Control management Slow Control serial link: For various parameters (Gain, peaking time) & hit (or specific) channel read out Writing Mode 4 Signals (CMOS): Sc_din: input data Sc_ck: clock Sc_en: enable Sc_dout: output data Read out Mode

5. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 5 AGET: SCA management Control of the SCA mode: Write & read; 2 different CMOS signals Clock signals: 1 per SCA mode; Differential LVDS level SCA Manager SCA write 76 lines 511 cells SCA read Clk write Clk readR Vreturn:0,7V In Bufferout W CLKwrite CLKread Write Read Write phase Read phase

6. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 6 AGET: TEST management TEST: 3 different modes (Slow Control) Signals: 2 analog input signals: 1 in current & 1 in voltage selj seli x72 Pulse Generator ASIC selj seli x72 Pulse Generator ASIC X3 (1/Charge range) Pulse Generator selj seli x76 ASIC Calibration Test Functional

7. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 7 AGET: Analog Data management T2K: 12-bit ADC [AD9229]; Fckread = 20 MHz ADC Bus ana 3 Bus ana 2 Bus ana 1 Bus ana 0 18 cm The functionality of AFTER + ADC has been proved (TPC & FGD T2K projects)

8. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 8 GET:12-bit ADC [ADS6422]; Fckread = 25 MHz ADC Input Sampling Circuit 10pF 10pF AFTER Buffer AGET: Analog Data management Vdiff Simulation Sampling Switch on 1.45V 2 mA 1 & 2 mA (Ibuff: 15.35mA to 24.41 mA) 1.5V2.2V1ns 1ns 50ns 0.7V The settling time of the signal can be “controlled” by the reference current Vgg7 (output bias) Question: Where does the ADC sample the data ? [Tckread/2 for Sample & Tckread/2 for hold ?]

9. ASAD Workshop Saclay (CEA Irfu) November 25, 2008 9 Trigger: Σ 72 discriminators AGET: Trigger management AGET_trigger+ AGET_trigger- Σ 72 discriminators Signal: analog current differential output Output dynamic: 72 * N µA per outputMust be defined Minimum signal width: 80 ns+/- 15% Receiver: The solution for the trigger management will define the output specifications needed for the output signal (Output common mode voltage, settling time, dynamic..) Receiver C? Vicm? AGET Zin?