1. LHCb Outer Tracker Upgrade Actel FPGA based Architecture 117 januari 2013 Outline ◦ Front end box Architecture ◦ Actel TDC ◦ Data GBT interface ◦ Data format ◦ Test Setup ◦ AMC40 test setup Antonio Pellegrino, Tom Sluijk, Wilco Vink,

2. Front-end box architecture 217 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

3. Front-end box 3 ◦ 1 GBT master/power board (replaces: GOL board)  Versatile link transceiver, Master GBT  TFC signals  1 SCA for monitoring (power, temperature, etc.)  8 Optical data transmitters  4 dual transmitters versatile link OR  12-way optical transmitter, based on KK Ghan’s vcsel driver (8+4 spare)  Power supplies based on CERN SM01C DC/DC conv. ◦ 4 Actel TDC boards (replaces: OTIS boards)  2 data transmitter GBT’s  Wide bus format data transmitters  One used for clocks, BxClk TpClk, TFC,clk  Spare clocks for TDC  1 SCA  Actel re-programming via JTAG  GBT configuration  4 Threshold DAC  Temperature monitoring  Soft reset Actel  1 Actel Pro-asic A3PE1500  32 channel, 5-bits TDC  Zero suppression ◦ 8 ASDBLR boards (unchanged) 17 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

4. Actel TDC 4 Pro-Asic A3PE1500 (4 FPGA’s/FE-box) 32 channel 5 bits TDC ◦ Based on 4 320 MHz clocks(2 edges and 90phase shifted) ◦ fixed placement (3 variants: top right bottom) Zero suppression 17 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

5. Two options uses identical PCB, different Actel firmware ◦ 8 Data GBT’s per FE-box  One ZS output bus per 16 channels  No bandwidth limitations  NZS full bandwidth readout possible ◦ 4 data GBT’s per FE-box  One ZS output bus per 32 channels  Bandwidth limit, lower cost Wide-bus GBT format 28b@160MHz Data GBT interface 517 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

6. Two 16 ch. TDC in one FPGA Dual GBT’s 6 16 channel TDC Zero-supp 16 stages ReadoutGBT1Fifo Actel FPGA 16 channel TDC Zero-supp 16 stages FifoReadoutGBT2 Data Format (9 channels hit): Padded ‘0’ 8 bits Status4 bits BX cnt16 bits Hit pattern channel (0-15) 027 5 bits Data Padded ‘0’ 8 bits Status4 bits BX cnt16 bits Hit pattern channel (16-31) 5 bits Data GBT2 GBT1 Max 4 words when all channels are hit 17 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

7. 32 channel TDC with single GBT 7 32 channel TDC Zero-supp 32 stages ReadoutGBTFifo Actel FPGA Data Format (9 channels hit): 8 bits Status4 bits BX cnt16 bits Hit pattern channel (0-15) 16 bits Hit pattern channel(16-31)Data 5 bits Data 5 bits5 bits Data 5 bits DatPadded ‘0’ s 027 5 bits Data Max 8 words when all channels are hit 17 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink, GBT

8. OTTOv2 Test Setup 8 StratixIV 230 evaluation board Dummy GBT, based on code Sophie baron Not yet implemented Small TFC Data buffer (512MB DDR3) I2C over Ethernet, dummy ECS/SCA OT TDC to Optical: OTTOv2 Prototype board with combined TDC board (OTIS) and Master GBT board (GOL) Actel TDC Snap 12 optical receiver/transmitter Versatile link: Dual transmitter (data GBT) Bi-directional (master GBT) SM01C radiation hard DC/DC power converters SCA Mezzanine (SCA pin-out not known) Threshold DAC 17 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

9. Test setup 917 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

10. Test Setup 10 ASDBLR left ASDBLR right Actel TDC SCA Snap12 Rx Snap12 Tx Vers.Link Power Altera Dummy GBT slaveAltera Dummy GBT master 1GbEth 17 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

11. OTTO with master/slave StratixIV ◦ Data GBT emulated ◦ Master GBT  TFC signals  ECS via E-Link to SCA ◦ dev.brd as 1/4 Front end box ◦ Needs GBT wide-bus FPGA code (S.Baron) AMC40 used for DAQ and TFC/ECS ◦ Needs AMC 40 firmware  TFC/ECS  OT data format, DAQ interface to 10GbE ◦ PC control software available?  ECS/TFC (PVSS CCPC GBT SCA OTTO)  DAQ->data-storage Test setup with AMC40 1117 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,

12. AMC40 test setup overview 1217 januari 2013Antonio Pellegrino, Tom Sluijk, Wilco Vink,