1. Serial Power Distribution for the ATLAS SCT Upgrade John Matheson Rutherford Appleton Laboratory On behalf of the SP Community Thanks to Richard Holt (RAL), Dave Lynn (BNL) and Peter Phillips (RAL)

2. 2 Outline the SCT upgrade powering issues for the SCT upgrade the serial powered detector stave concept SP implementations in more detail a practical SP stave architecture SP stave test results (ABCD FEICs) test results with ABCnext FEICs test results with SPI (serial power interface ASIC) work in progress and in future summary and conclusions

3. 3 present ATLAS SCT: 4088 detector modules 3.2M channels upgrade SCT: need 34 M channels to cope with increased luminosity 768 chan/side current SCT module design The present SCT

4. 4 Powering the present SCT 4088 Detector Modules Independent Powering –4088 cable chains –22 PS racks –4 crates / rack –(up to) 48 LV and 48 HV channels / crate Overall efficiency ~40% –Cable R => voltage drops

5. 5 layout of the Upgraded SCT detector staves arranged into barrels detector petals arranged into discs

6. 66 The SP stave concept staves carry 12 detectors, 24 readout modules each module carries 20 ABCn ROICs a serial powering chain is a natural option each module must carry a shunt regulator to keep supply V constant powering by DC-DC converters is a competing option, or a complementary option

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8. 8 Shunt Regulator Architectures Hybrid with Shunt “W” Use each ABCN’s integrated shunt regulator Use each ABCN’s integrated shunt transistor(s) Hybrid with Shunt “M” Use one external shunt regulator Use each ABCN’s integrated shunt transistor(s) –Two (redundant) shunt transistors, 140mA each Hybrid with SPi (or similar) Use one external shunt regulator Use one external power transistor All now available in silicon: final choice to be based upon test results.

9. 9 Eff = 55% Eff = 50% D H Lowest Noise: SP with on-chip Linear Regulators for both Analogue and Digital SP Options in more detail Highest Efficiency: SP with on-chip DC-DC conversion using switched capacitors Eff = 77% Eff = 75% D H Efficiency = power delivered to hybrid H power consumed by ABCN Efficiency = power consumed by ABCN D power delivered by power supply Some assumptions: Cable resistance 2 ohms for each line pair, SR = 85%, low current DC-DC = 90%, high current DC-DC = 85% Bus cable traces 7.5mm wide, 18 micron Cu chip power is that projected for 130nm ABCn ABCN demand power is dependent on task. This will normally mean a shunt regulator will dissipate some power to maintain voltage under all conditions.

10. 10 Comparison – DCDC, IP Eff = 76% Eff = 40% Eff = 100% Eff = 1% Off-chip DC-DC conversion from 10V to 2.4V and 1.8V (assume 85% efficiency) “On-chip” DC-DC conversion using switched capacitors (assume 90% efficiency) Independent Power D H D H With ABCN in 130 nm technology, we shall study the options to obtain the best trade-off between efficiency and performance…

11. 11 SP Stave Architecture 24 hybrids in series, each at different potential wrt GND CLK & COM AC coupled at hybrid DATA AC coupled at end of stave Common GND at end of stave (DC-DC powered stave would look similar, apart from the absence of AC coupled IO)

12. 12 Protection of SP against faults Whilst demonstration staves have generally been reliable: What happens if a module fails open circuit? What happens if a module becomes a noise generator? How to turn modules on/off? We could provide a system to “short out” each module under control of DCS Voltage across shorted module should be small (<100mV) Area of components and number of control lines must be small Automatic over current and over voltage protection is desirable Protection circuit must draw no (minimal) power when module active Ability to put modules into “stand by” (low power state)

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14. 14 AC coupled data transmission - prototype bus tape Test stave at Oxford Cu/kapton + Al screen layer Send “TTC” data from FPGA  24 dummy hybrids with receiver/drivers Loopback data on dummy hybrids  FPGA  BERT. Measure BERT for balanced and unbalanced data, parallel and serial powering Balanced code works fine. M-LVDS + Serial powering + balanced code ok, ie no errors found in 3 locations tested (3,12 and 24). Whether we use SP or not, need to minimize number of signal traces in stave => multi-drop

15. 15 Serial Powering is compatible with the use of a single HV supply for several modules Each sensor is dynamically connected to current source ground through output impedances of the chain of shunt regulators Low shunt output impedance is crucial to achieve good ‘grounding’ and reduce noise Standard HV powering: one HV per moduleAlternative HV powering: one HV supply per M modules Serial Powering and HV

16. 16 30 * 4V = 120V (ABCD, 800nm) Stave07: 30 module stave with ABCD System tests of SP staves – Stave 07 Future: 24 * ~1V = 24V for 130nm ABCN We have verified that: 1.Noise is not an issue 2.AC coupled (M)LVDS works 3.SP uses little extra real estate 4.Can use single HV line / strip stave stave working well ! Thick Film Hybrid for 6 ABCD chips with integrated Serial Powering circuitry: requires ~0.75A at 4V

17. 17 ABCD Noise Slope SCT Barrel Module Bare Chip SP does not increase noise ! independent powering independent powering serial powering

18. 18 First tests of integrated shunts in ABCN: RAL single chip PCB and Liverpool Hybrid this is the most recent generation of FEIC: ABCn in 250nm CMOS next step: ABCn in 130nm CMOS

19. 19 Single Chip using shunt “M” IP result 380 ENC: SAME!

20. 20 ABCN hybrid using shunt “W” PRELIMINARY ENC 450 e- RMS

21. 21 What is SPi? SPi (Serial Power Interface): Shunt regulator schemes Data communication Power management Monitoring/alarms Designed by Marcel Trimpl (FNL) Mitch Newcomer (U Penn) 2.7 mm 5.5 mm  flip chip, bump bonded  144 pads (68 I/O, 76 power)  Sub-set used for each application

22. 22 Example tests on SPI Communication works well Power line Control clock Data out Data in Programmable shunt regulator OK Programmable linear regulators (mostly) work reliably

23. 23 SPi with a hybrid SPi = “Serial Powering interface”…  Shunt regulator schemes  ABCN with SPi internal shunt regulator  ABCN with SPi controlling distributed shunt transistors  Data communication  Data has passed through SPi  Power management  Shunt current monitoring  Shunt regulator voltage setting  Linear regulators voltage setting  Alarm  = tested and working Documentation is available to users

24. 24 The Stavelet ATLAS community stavelets are planned Allows comparison of different power configurations Different bus cable designs Different grounding and shielding concepts Stavelets early 2010, realistic stave late 2010 ? Stavelets allow option choices The power plug-in concept DistributedSPiDC-DC Data & hybrid communication Power & power control communication (SPi)

25. SP Summary and Next Steps Staves have been built with commercial SP components Shunt circuitry has now been integrated into FE chips Protection can be part of SP architecture AC coupling works well with balanced codes HV distribution is understood A custom current source is available First ABCN demonstrator stavelet planned for this year –Integrated shunts + protection – Possibility of testing different SP, G+S options Will be used to choose options for Stave09 SP is an attractive option for sLHC power distribution

26. 26 Spare slides

27. 27 Digital: Analogue: ABCD (0.8  m, biCMOS) 4.0 volts 3.5 volts 35 mA per chip (actual) 74 mA per chip (actual) => 4.0 x 35 + 3.5 x 74 = 399 mW Digital: Analogue: ABCN13 (0.13  m CMOS) 0.9 volts 1.2 volts 51 mA per chip (estimate) 16 mA per chip (estimate) => 0.9 x 51 + 1.2 x 16 = 65 mW Digital: Analogue: 2.5 volts 2.2 volts 95 mA per chip (preliminary) 27 mA per chip (preliminary) => 2.5 x 95 + 2.2 x 27 = 300 mW ABCN25 (0.25  m CMOS) In ATLAS SCT Present Prototype Proposed ** Power Estimates for an ABCN in 130nm Technology, Mitch Newcomer, Atlas Tracking Upgrade workshop, NIKHEF, November 2008 http://indico.cern.ch/getFile.py/access?contribId=16&sessionId=8&resId=0&materialId=slides&confId=32084 Power per 128 channel chip per channel 3.1 mW 2.3 mW 0.5 mW ** Power Requirements with Modern Process Technologies ABCN25: Vdig > Vana Idig >> Iana If we generate Vana from Vdig using LR: 27mA * 0.3V = 8.1mW per chip 3% of chip power ABCN13: Vana > Vdig Idig >> Iana If we generate Vdig from Vana using LR: 95mA * 0.3V = 28.5mW per chip 44% of chip power Can we do better than this? Of course…

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29. 29 Definition – Hybrid (excludes stave interconnects & supply cables) Efficiency = H power delivered to hybrid power consumed by ABCN Definition – Detector (includes all supply cables) Efficiency = D power delivered by power supply power consumed by ABCN Some assumptions: Cable resistance 2 ohms for each line pair, SR = 85%, low current DC-DC = 90%, high current DC-DC = 85% ABCN demand power is dependant on task. This will normally mean a shunt regulator will dissipate some power to maintain voltage under all conditions. Efficiency - definitions Efficiency D H

30. 30 Independent powering (100% hybrid efficiency) 1 stave = 24 hybrids = 480 ABC- N (0.13  m) 32 Watts 0 Watts 3 Watts Numbers rounded 2668 Watts Efficiency = 1% D Power (voltage) 2633 Watts Independent supplies (line pairs) for digital and analogue power. Same amount of copper => Cables are 96 ohms total for each line pair. Each line pair carries 20 x 51mA (digital) and 20 x 16mA (analogue). Detector power efficiency

31. 31 Serial powering 3.6V, 3:1 & 4:1 DC-DC using switched capacitors 1 stave = 24 hybrids = 480 ABC- N (0.13  m) Numbers rounded Power (constant current) Regulator power = (1/eff - 1) x ABC power H Stave supply current = (32 + 9.6 + 0.5)watts / (3.6volts x 24) = 0.49amps Detector power efficiency 32 Watts 9.6 Watts 0.5 Watts Cables assumed to be 2 ohms total for each power line pair (77% efficiency ) H 0.5 Watts 43 Watts Efficiency = 75% D

32. 32 Richard Holt – Rutherford Appleton Laboratory Combined SP & DC-DC powering options November 2008 Detector power efficiency Two-stage DC-DC powering (78% hybrid efficiency) 17 1 stave = 24 hybrids = 480 ABC- N (0.13  m) 32 Watts 9 Watts 1.3 Watts Numbers rounded Power (voltage) Cables assumed to be 2 ohms total for each power line pair (78% efficiency ) H Regulator power = (1/eff - 1) x ABC power Stave supply current = (32 + 9)watts / 10volts = 4.1amps 76 Watts Efficiency = 42% D 34 Watts

33. 33 Richard Holt – Rutherford Appleton Laboratory Combined SP & DC-DC powering options November 2008 Serial powering a stave, (no DC-DC version) 18 1 stave = 24 hybrids = 480 ABC- N (0.13  m) Numbers rounded Power (constant current) Regulator power = (1/eff - 1) x ABC power H Stave supply current = (32 + 14)watts / (1.2volts x 24) = 1.6amps Detector power efficiency 32 Watts 14 Watts 0.5 Watts Cables assumed to be 2 ohms total for each power line pair (70% efficiency ) H 5.1 Watts 52 Watts Efficiency = 62% D

34. 34 Richard Holt – Rutherford Appleton Laboratory Combined SP & DC-DC powering options November 2008 Serial powering a stave, (higher voltage, with DC-DC version) 19 1 stave = 24 hybrids = 480 ABC- N (0.13  m) Numbers rounded Power (constant current) Regulator power = (1/eff - 1) x ABC power H Stave supply current = (32 + 8.5)watts / (1.6volts x 24) = 1.1amps Detector power efficiency 32 Watts 8.5 Watts 0.5 Watts Cables assumed to be 2 ohms total for each power line pair (79% efficiency ) H 2.4 Watts 43 Watts Efficiency = 74% D

35. 35 SP and Endcap Geometries The baseline design for the endcap of an upgraded ATLAS strip detector is based around petals. Not all hybrids have the same number of chips –Group hybrids with similar numbers of chips into their own power chains Chain 1: (3*16) chip units Chain 2: (4*12)+(2*10) chip units –Additional current corresponding to two chips must be dissipated by the shunt(s) on each 10 chip hybrid. Efficiency depends upon the values of the analogue and digital voltages and the means used to generate them: –Example: 3 ohm cable pair, 1.5V supply, 140mA per chip and 85% shunt efficiency => 54% efficiency –GOOD ENOUGH

36. 36 SP Module Architecture Module Controller Chip (MCC) Functions common to SP & DC-DC multiplexes 2 data streams into 1 voltage monitoring Additional for SP powered by SP AC coupling of CLK & COM Requires 4 capacitors Everything else on chip Temperature read by (stave end) DCS Monitor T before power applied Shunt protection under DCS control Turn on modules independently SP requires minimal extra circuitry at the module end SP extras

37. 37 Scan point Occupancy Thirty Module Stave: Some Results S-curve VT50 (mV) Gain (mV/fC) Output Noise (mV) Input Noise (ENC) Input Noise (ENC) Channel number Threshold (mV)

38. 38 Example tests Data communication +Works reliably +Can change direction +Can change drive current 50 MHz clock, Showing LVDS inputs and outputs 3.65 ns delay Richard Holt – Rutherford Appleton Laboratory SPi test results September 2009

39. 39 Example tests Current measurement +Works reliably - Not perfectly linear Richard Holt – Rutherford Appleton Laboratory SPi test results September 2009