1. ARM organization

2. ARM single-cycle instruction pipeline operation

3. ARM multi-cycle instruction pipeline operation

4. ARM9TDMI 5-stage pipeline organization

5. Data processing instruction datapath activity

6. STR (store register) datapath activity

7. The first two (of three) cycles of a branch instruction

8. 2-phase non-overlapping clock scheme

9. ARM datapath timing

10. The original ARM1 ripple-carry adder circuit

11. The ARM2 4-bit carry look-ahead scheme

12. The ARM2 ALU logic for one result bit

13. ARM2 ALU function codes

14. The ARM6 carry-select adder scheme

15. The ARM6 ALU organization

16. ARM9 carry arbitration encoding

17. The cross-bar switch barrel shifter principle
right 3
right 2
right 1
no shift
in[3]
left 1
in[2]
left 2
in[1]
left 3
in[0]
out[0]
out[1]
out[2]
out[3]

18. The 2-bit multiplication algorithm, Nth cycle

19. Carry-propagate (a) and carry-save (b) adder structures

20. ARM high-speed multiplier organization

21. ARM2 register cell circuit

22. ARM register bank floorplan

23. ARM core datapath buses

24. ARM control logic structure