1. 1 CS 352 Introduction to Logic Design Lecture 5 Ahmed Ezzat Multiplexers, Decoders, Programmable Logic Devices, and Intro to VHDL Ch-9 + Ch-10

2. CS-352Ahmed Ezzat 2 Outline Introduction Multiplexers Three-State Buffers Decoders and Encoders Read-Only Memories Programmable Logic Devices – Programmable Logic Arrays – Programmable Array Logic Complex Programmable Logic Devices Field Programmable Gate Arrays – Decomposition of Switching Functions VHDL Description of Combinational Circuits VHDL Models for Multiplexers VHDL Modules Signals and Constants Arrays VHDL Operators Packages and Libraries IEEE Standard Logic Compilation and Simulation of VHDL Code

3. CS-352Ahmed Ezzat 3 Introduction We will transition from basic logic design to more complex integrated circuits (ICs) in logic design. ICs are classified into: – Small-scale integration (SSI): 1 - 4 gates, inverters and F/Fs – Medium-scale integration (MSI): such as adders, multiplexers, decoders, registers, and counters. Typically 12 – 100 gates – Large-scale integration (LSI): typically contains 100 to few thousands gates. – Very-large-scale integration VLSI): typically contains several thousands gates or more.

4. CS-352Ahmed Ezzat 4 Multiplexers Multiplexers (MUX) has group of data inputs and a group of control inputs. The control inputs select one of the data inputs and connect it to the output. Z = A’I 0 + AI 1 Z = A’B’I 0 + A’BI 1 + AB’I 2 + ABI 3 Z = Σ m k I k K=0 2 n - 1

5. CS-352Ahmed Ezzat 5 Three-State Buffers (1) Typically a gate is connected to a limited number of other gate inputs unless using a buffer in between to increase the driving capability of the gate output. 3-state buffer permits the outputs of 2 or more gates to be connected together:

6. CS-352Ahmed Ezzat 6 Three-State Buffers (2) The following shows a three-state buffer and its logical equivalent: – B = 1  C = A – B = 0  Hi-Z (open circuit)

7. CS-352Ahmed Ezzat 7 Three-State Buffers (3) Truth table for 4-types of three-state buffers:

8. CS-352Ahmed Ezzat 8 Three-State Buffers (4) Two three-state buffers can be tied together to function as a 2:1 multiplexer D = B’A + BC

9. CS-352Ahmed Ezzat 9 Decoders and Encoders (1) Decoder generates all minterms for all possible n-inputs.

10. CS-352Ahmed Ezzat 10 Decoders and Encoders (2) Decoder logic diagram:

11. CS-352Ahmed Ezzat 11 Decoders and Encoders (3) Encoder performs the inverse of a decoder. Example is the 8-3 priority encoder. (y 0  y 7  abc). If more than one input (y 1, y 4 ) is 1, only the highest number will be encoded (y 4 ). X in table means don’t care. Output d is 1 if any input is 1, otherwise d is 0.

12. CS-352Ahmed Ezzat 12 Read-Only Memories (1) ROM is an array of semiconductor devices that stores an array of binary data.

13. CS-352Ahmed Ezzat 13 Read-Only Memories (2) ROM is basically a decoder and a memory array. When a pattern of 0s and 1s is applied as input, exactly one of the 2 n decoder outputs is 1. This active output will select one word from the memory array of words, and the bit pattern in that word is made available to the memory output lines.

14. CS-352Ahmed Ezzat 14 Programmable Logic Devices (1) PLD is an IC that is programmable to provide a variety of different logic functions. Several types of combinational PLDs in additional to sequential PLDs. Simple combinational PLD is capable of realizing from 2 – 10 functions of 4 – 16 variables within one IC. More complex PLDs may contain thousands of F/Fs, gates, etc. PLDs facilitate easy way of changing digital circuit design with lower cost.

15. CS-352Ahmed Ezzat 15 Programmable Logic Devices (2) Programmable Logic Arrays (PLA) PLA is similar to ROM. PLA can have n-inputs (variables) and m-outputs (functions). Internals of PLA is different from that of ROMs.

16. CS-352Ahmed Ezzat 16 Programmable Logic Devices (3) Programmable Logic Arrays (PLA) PLA with 3-inputs, 5 product terms, and 4 outputs

17. CS-352Ahmed Ezzat 17 Programmable Logic Devices (4) Programmable Logic Arrays (PLA) Equivalent AND-OR circuit to the previous PLA:

18. CS-352Ahmed Ezzat 18 PAL is a special kind of PLA in which the AND array is programmable and the OR array is fixed. PAL is less expensive than the general purpose PLA, and PAL is easier to program as well. Programmable Logic Devices (5) Programmable Array Logic (PAL) Unprogrammed Segment in PAL Programmed Segment in PAL

19. CS-352Ahmed Ezzat 19 Realize the function: F = I 1 I 2 ’ + I 1 ’I 2 Programmable Logic Devices (6) Programmable Array Logic (PAL)

20. CS-352Ahmed Ezzat 20 Complex Programmable Logic Devices (CPLD) CPLD is a set of interconnected PALs or PLAs on a single chip. With storage elements included, a small digital system can be implemented on a single CPLD.

21. CS-352Ahmed Ezzat 21 Field Programmable Gate Arrays (1) FPGA is an IC that contains an array of identical logic cells with programmable interconnections. User can program the function performed by each cell as well as the interconnection between cells.

22. CS-352Ahmed Ezzat 22 Field Programmable Gate Arrays (2) Example of a Configurable Logic Block (CLB): A function generator (4-inputs) is implemented as lookup table  H Multiplexer (selects F or G depending on value of H 1 )  X, Y, XQ, YQ are selected by programmable multiplexers.

23. CS-352Ahmed Ezzat 23 Field Programmable Gate Arrays (3) Decomposition of Switching Functions We need to decompose functions with large number of variables into subfunctions with each requires less variables. Shannon’s Expansion Theorem: F(a,b,c,d) = a’F(0,b,c,d) + aF(1,b,c,d) = a’F 0 + aF 1 Example: F(a,b,c,d) = c’d’ + a’b’c + bcd + ac’ F(a,b,c,d) = (a’c’d’ + ac’d’) + a’b’c + (a’bcd + abcd) + ac’ = a’(c’d’ + b’c + bcd) + a(c’d’ + bcd + c’) = a’(c’d’ + c(b’ + bd)) + a[c’(d’ + 1) + bcd] = a’(c’d’ + c((b’ + d)(b + 1))) + a[c’ + bcd] = a’(c’d’ + b’c + cd) + a[(c’ + bd)(c + 1)] = a’(c’d’ + b’c + cd) + a(c’ + bd) = a’F 0 + aF 1 Both F 0, F 1 are 2-variable functions

24. CS-352Ahmed Ezzat 24 Field Programmable Gate Arrays (4) Decomposition of Switching Functions General Form for Shannon’s Expansion Theorem: F(x 1,x 2,…x i-1,x i,x i+1, …., x n ) = x i ’F(x 1,x 2,…x i-1,0,x i+1, ….,x n ) + x i F(x 1,x 2,…x i-1,1,x i+1, ….,x n ) = x i ’F 0 + x i F 1

25. CS-352Ahmed Ezzat 25 VHDL Description of Combinational Circuits (1) Design very complex circuits at the gate and F/F level can be very tedious and time consuming. As a result, using a hardware description language to design and debug a complex circuit at high-level before implementation at the gate level becomes very important. Use of CAD tools is becoming essential with complex circuits. Good analogy is writing a program in high-level language (such as C) and use compiler to convert it to machine language. VHDL is used to describe the behavior and structure of a digital system. VHDL stands for “VHSIC Hardware Description Language”; where VHISC stands for “Very High Speed Integrated Circuit.”

26. CS-352Ahmed Ezzat 26 VHDL Description of Combinational Circuits (2) Assume propagation delay in a gate = 5 nsec. The symbol “<=“ is the signal assignment operator Signal_name <= expression [after delay];

27. CS-352Ahmed Ezzat 27 VHDL Description of Combinational Circuits (3) Unlike a sequential program, the order of the above concurrent statements is unimportant. VHDL program has no explicit loops, however a statement may execute repeatedly as if they were in a loop.

28. CS-352Ahmed Ezzat 28 VHDL Description of Combinational Circuits (4) Examples:

29. CS-352Ahmed Ezzat 29 VHDL Description of Combinational Circuits (5) Examples: Array of AND Gates

30. CS-352Ahmed Ezzat 30 VHDL Models for Multiplexers (1) MUX output can be expressed as: – MUX: F = A’.I 0 + A.I 1 – Conditional signal assignment: – General form of conditional signal statement is: signal_name <= expression1 when condition1 else expression2 when condition2 else expressionN; F <= (not A and I 0 ) or (A and I 1 )

31. CS-352Ahmed Ezzat 31 VHDL Models for Multiplexers (2) Cascaded 2-to-1 Muxes:

32. CS-352Ahmed Ezzat 32 VHDL Models for Multiplexers (3) Cascaded 4-to-1 Muxes: F = A’B’I 0 + A’BI 1 + AB’I 2 + ABI 3 Model-1: Model-2: F <= I 0 when A&B = “00” else I 1 when A&B = “01” else I 2 when A&B = “10” else I 3 ; F <= (not A and not B and I 0 ) or (not A and B and I 1 ) or (A and not B and I 2 ) or (A and B and I 3 )

33. CS-352Ahmed Ezzat 33 VHDL Modules (1) A complete VHDL module must declares all input and output signals using entity declaration, and then specify the internal operations of the module using an architecture declaration. Port is input/output to the module Signal C is an internal signal 2 concurrent statements that describe the gates are placed between the keywords begin and end

34. CS-352Ahmed Ezzat 34 VHDL Modules (2) In VHDL, we must specify an entity & architecture for each module in the circuit. Each entity includes a list of interface signals that connect to other modules or to outside the circuit. Interface signal declaration may have type and initial value. An entity declaration may have 0 or more interface signal declarations. Associated with each entity is one or more architecture declarations.

35. CS-352Ahmed Ezzat 35 VHDL Modules (3) entity entity-name is [port (interface-signal-declaration);] end [entity] [entity-name]; List-of-interface-signals: mode type [: = initial-value] {;List-of-interface-signals: mode type [: = initial-value]}; Curly brackets indicate 0 or more repetitions of the enclosed clause. Ex: port(A, B: in integer : = 2; C, D: out bit); A, B are input signals of type integer that are initially set to 2, and C and D are output signals of type bit that are initialized by default to ‘0’. architecture architecture-name of entity-name is [internal signal declarations] begin architecture body end [architecture] [architecture-name];

36. CS-352Ahmed Ezzat 36 VHDL Modules (4)

37. CS-352Ahmed Ezzat 37 VHDL Modules (5) Four-bit Full Adder

38. CS-352Ahmed Ezzat 38 Signals and Constants (1) Input and output signals are declared in a port. Internal signals to a module are declared at the start of an architecture (i.e., before begin). Port signals have an associated mode (usually in or out), but internal signals do not. Signal declaration takes the form: Constraint can be an index range like (0 to 5) or (4 downto 1), etc. Constants can be declared then used within the architecture body: constant constant_name: type_name [constraint] [:constant_value] constant delay1 : time := 5 ns; Usage: A <= B after delay1; Signal list-of-signal-names: type-name [constraint] [:= initial_value];

39. CS-352Ahmed Ezzat 39 Signals and Constants (2) Predefined Types bit – “0’ or ‘1’ boolean – TRUE or FALSE integer – range of –(2 31 -1)  +(2 31 -1) positive – range of 1  (2 31 -1) natural – integer in range of 0  (2 31 -1) real – floating point in range -1.0E38  +1.0E38 character – any legal HDL character including lower and upper case, digits, and special characters time – an integer with units: fs, ps, ns, us, ms, sec, min, or hr

40. CS-352Ahmed Ezzat 40 Arrays (1) Needs to declare the array before using it: SHORT_WORD is an array of size 16 entries, and each entry is a bit Usage Examples: signal DATA_WORD: SHORD_WORD signal ALT_WOD: SHORT_WORD := “0101010101010101”; constant ONE_WORD: SHORT_WORD := (others => ‘1’); We can reference individual entries in the array, e.g., ALT_WORD(0) accesses the far right bit in ALT_WORD. Type SHORT_WORD is array (15 downto 0) of bit;

41. CS-352Ahmed Ezzat 41 Arrays (2) Multidimensional arrays are supported: type matrix4x3 is array (1 to 4, 1 to 3) of integer; signal matrixA: matrix4x3 := ((1,2,3),(4,5,6),(7,8,9),(10,11,12)); MatrixA will be initialized as follows: A(3,2) will reference the element in 3 rd row and 2 nd column, which has value of 8. Unconstrained array (declared array without defining its dimensions): type intvec is array (natural range <>) of integer; intvec is one dimensional array of type integers with unconstrained index range of natural numbers. type matrix is array (natural range <>, natural range <>) of integer; type string is array (positive range <>) of character; constant string1:string (1 to 29) := “This string is 29 characters.” constant A : bit_vector(0 to 5) := “101011”; 1 2 3 4 5 6 7 8 9 10 11 12

42. CS-352Ahmed Ezzat 42 VHDL Operators Predefined VHDL operators can be grouped into 7 classes: – binary logical operators: and or nand nor xor xnor – relational operators: = /= >= – shift operators: sll (shift left logical) srl sla (shift left arithmetic) sra rol (rotate left) ror – adding operators: + - & (concatenation) – unary sign operators: + - – multiplying operators: * / mod (modulo) rem (remainder) – miscellaneous operators: not abs ** (raises integer or floating – point number to an integer power)

43. CS-352Ahmed Ezzat 43 Packages and Libraries (1) VHDL provides means to group functions into packages and defines libraries to enable accessing them from multiple VHDL designs. Package consists of declaration and body Package declaration may be shared by several design units. Typically will contain: type, signal, component, function, and procedure declaration. Package body contains component description, function and procedure bodies. A package and its associated compiled VHDL models may be placed in a library, so they can be accessed by different VHDL designs.

44. CS-352Ahmed Ezzat 44 Packages and Libraries (2) Package declaration: package package_name is package declaration end [package] [package_name]; package body: package body package_name is package body declaration end [package body] [package_name]; component Nor2 // Nor2 is a component that is a NOR gate port (A1, A2: in bit; Z: out bit); end component;

45. CS-352Ahmed Ezzat 45 Packages and Libraries (3) NOR gate is modeled using a concurrent statement. The entity-architecture pair for this component is: entity Nor2 is port (A1, A2: in bit; Z: out bit); end Nor2; architecture concur of Nor2 is begin Z <= not(A1 or A2) after 10 ns; end concur To access the above component we need the library and use statements: library BITLIB; // library stmt to allow access to the package use BITLIB.bit_pack.all; // bit_pack is the package name use BITLIB.bit_pack.Nor2; // Nor2 from the bit_pack package

46. CS-352Ahmed Ezzat 46 Packages and Libraries (4) NOR-NOR Circuit and Structural VHDL Code Using Library Components

47. CS-352Ahmed Ezzat 47 IEEE Standard Logic (1) Use of 2-valued logic (bits and bit vectors) is not adequate for simulation of digital systems. In addition, values of ‘Z’ (no connection or High impedance) and ‘X’ (unknown) are frequently used. IEEE standard 1164 defines a “std_logic” type that actually has nine values: U, X, 0, 1, Z, W, L, H, and _). We will use only the first 5 values. ‘U’ stands for uninitialized.

48. CS-352Ahmed Ezzat 48 IEEE Standard Logic (2) In order to use signals of type std_logic and std_logic_vector in a VHDL module, we need to place the following declarations before the entity declaration: library ieee; use ieee.std_logic_1164.all;

49. CS-352Ahmed Ezzat 49 IEEE Standard Logic (3) Addout is a 5-bit sum that is split into Sum and Cout.

50. CS-352Ahmed Ezzat 50 Compilation and Simulation of VHDL Code (1) Simulation: is important to: – Verify the VHDL code correctly implements the intended design. – Verify that the design meets its specifications. Before simulation, we need to compile the VHDL code (VHDL compiler is also called analyzer): – Compiler checks the source code for syntax and semantics rules. – Compiler checks that references to libraries are correct. – Compiler generates intermediate code which can be used by the simulator or by a synthesizer. After compilation, we need to convert the intermediate code to a form that can be used by the simulator (elaboration). During elaboration, ports are created for each instance of a component, memory storage is allocated for the required signals, interconnections between port signals are specified, and prepared for execution in the proper sequence.

51. CS-352Ahmed Ezzat 51 Compilation and Simulation of VHDL Code (2) After initialization phase, the simulator enters execution phase. Simulator accepts commands which control the simulation of the digital system, and specify the desired output.

52. CS-352Ahmed Ezzat 52