1. Grzegorz Kasprowicz1 Level 1 trigger sorter implemented in hardware

2. Grzegorz Kasprowicz2 LHCb readout architecture D etector L0 FE VELO L0 FE STOT RICH ECALHCALMUON SWITCH L1 FE SWITCH SFC SWITCH CPUCPU READOUT NETWORK CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU CPUCPU TFC SYSTEM L0 TRIGGER LHC CLK 40 MHz 1 MHz 40 KHz SORTER Two levels of high-rate triggers Front-End electronics Event building CPU farm

3. Grzegorz Kasprowicz3 Overview of the TFC architecture

4. Grzegorz Kasprowicz4 Function blocs and data flow of Readout Supervisor Q_L1 – trigger sorter block L1 DBUF - Data Buffer (SRAM) L0 ABUF - Accept Data Buffer (dual port SRAM) GbE RX – PM3386 chip based Gigabit Ethernet mezzanine board L1 LINK – TLK2501 – 1.6 GBPS transceiver

5. Grzegorz Kasprowicz5 L1 Trigger Sorter Tasks: Generation of control signals and receiving data from Ethernet mezzanine board Generation of control signals and receiving data from Ethernet mezzanine board Sorting triggers according to event id number Sorting triggers according to event id number Generation of control signals and data for TLK2501 transceiver Generation of control signals and data for TLK2501 transceiver Error detection – missing trigger, wrong event number range, timeout Error detection – missing trigger, wrong event number range, timeout Counting processed triggers Counting processed triggers Generating long and short trigger broadcasts for Q_MP Generating long and short trigger broadcasts for Q_MP Generating addresses and signals for Accept Trigger Buffer (L0) and L1 Data Buffer Generating addresses and signals for Accept Trigger Buffer (L0) and L1 Data Buffer

6. Grzegorz Kasprowicz6 How does it work? FPGA RX State machine TX state machine L1 Data Buffer (RAM) Ethernet Mezzanine Board Accept TRG Buffer (DPRAM) 1.6 GBPS transmitter (L1 Link) 6x32bit FIFO Error Detection L1 Link interface L1DBUF memory interface Accept TRG memory Interface Event number comparator DATA ADDR Control interface control DATADATA ADDRADDR DATADATA LBUS L0 DATA L1 TRG GBE From Readout Network TIMER control PLL BCLK RFCLK To FEE To Q_MP module

7. Grzegorz Kasprowicz7 Detailed description A RX state machine reads the L1 trigger decision packets from the GbE RX via a 32-bit 80 MHz bus. The state machine drops the ten 32- bit words of IP protocol and writes via FIFO the eight 32-bit words of L1 trigger data into the L1 DBUF using the Event ID as the address. A RX state machine reads the L1 trigger decision packets from the GbE RX via a 32-bit 80 MHz bus. The state machine drops the ten 32- bit words of IP protocol and writes via FIFO the eight 32-bit words of L1 trigger data into the L1 DBUF using the Event ID as the address. A TX state machine compares the L0 Event ID of the incoming L1 triggers with the L0 Event ID of the next trigger to broadcast stored in the L0 Accept Buffer. A TX state machine compares the L0 Event ID of the incoming L1 triggers with the L0 Event ID of the next trigger to broadcast stored in the L0 Accept Buffer. Upon receiving the next L1 trigger to broadcast, the state machine prepares the broadcast frame, transmits it together with a broadcast request to the TTC broadcaster in the Q_MP module. Upon receiving the next L1 trigger to broadcast, the state machine prepares the broadcast frame, transmits it together with a broadcast request to the TTC broadcaster in the Q_MP module. The state machine also ensures that the L1 trigger accept broadcasts are spaced by a minimum of 20  s and that the first L1 trigger reject broadcast after a L1 accept is transmitted after 900ns and otherwise at intervals of 400 ns. The state machine also ensures that the L1 trigger accept broadcasts are spaced by a minimum of 20  s and that the first L1 trigger reject broadcast after a L1 accept is transmitted after 900ns and otherwise at intervals of 400 ns.

8. Grzegorz Kasprowicz8 Simulations

9. Grzegorz Kasprowicz9 Summary This version, (not device optimized, with some safety margins) allows to achieve speed of sorting about 4 milion events per second, which leaves some safe margin This version, (not device optimized, with some safety margins) allows to achieve speed of sorting about 4 milion events per second, which leaves some safe margin It is much cheaper, takes much less place and consumes much less energy than previously used Network Processor based sorter, because needs only one FPGA + memory It is much cheaper, takes much less place and consumes much less energy than previously used Network Processor based sorter, because needs only one FPGA + memory GbE Interface card and L0 link transceiver will be mounted on RS board anyway GbE Interface card and L0 link transceiver will be mounted on RS board anyway