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Damu, 2008EGE535 Fall 08, Lecture 51 EGE535 Low Power VLSI Design Lecture #5 & 6 CMOS Inverter.

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Presentation on theme: "Damu, 2008EGE535 Fall 08, Lecture 51 EGE535 Low Power VLSI Design Lecture #5 & 6 CMOS Inverter."— Presentation transcript:

1 Damu, 2008EGE535 Fall 08, Lecture 51 EGE535 Low Power VLSI Design Lecture #5 & 6 CMOS Inverter

2 Damu, 2008EGE535 Fall 08, Lecture 52 Power Consumption Dynamic Dynamic Transition (Capacitor charge/discharge) Transition (Capacitor charge/discharge) Short-circuit Short-circuit Static Static Leakage Leakage P total =P dyn + P stat =P tran + P sc + P stat

3 Damu, 2008EGE535 Fall 08, Lecture 53 Transition Power: P tran (Charging C) v i (t) V DD C R on R off v o (t) i c (t)

4 Damu, 2008EGE535 Fall 08, Lecture 54 V DD C R i(t) i(t) v(t) dv dt ∫ ───── =∫ ── V DD – v RC v = V DD [1 - e ] - t ── RC i = C dv/dt =[V DD – v] /R dv V DD – v ── = ─────, dtRC - t ln [V DD – v] = ── + A RC Initial condition, t = 0, v = 0 → A = ln V DD i = i(t)v = v(t) V DD – v - t ln ───── = ── v DD RC [V DD – v] = V DD e - t ── RC Capacitor Charging Integrating V DD C R on v(t) i(t) 0V@t=0

5 Damu, 2008EGE535 Fall 08, Lecture 55 Energy Stored in Capacitor Energy stored in C Energy drain from V DD Energy dissipated in PMOS Tr V DD C R on v(t) i(t)

6 Damu, 2008EGE535 Fall 08, Lecture 56 Transition Power: Discharging C L V DD v i (t) CLCL R off R on v(t) i(t) CLCL R on v(t) i(t) v DD Energy dissipated in NMOS transistor (Energy loss in C)

7 Damu, 2008EGE535 Fall 08, Lecture 57 Summary: Transition Power Gate output rising transition Gate output rising transition Energy dissipated in pMOS transistor = CV 2 /2 Energy dissipated in pMOS transistor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Gate output falling transition Gate output falling transition Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated per transition = CV 2 /2 Energy dissipated per transition = CV 2 /2 Power dissipation: Power dissipation: P trans =E trans α f ck =α f ck CV 2 /2 α = activity factor (switching activity)

8 Damu, 2008EGE535 Fall 08, Lecture 58 Components of Power Dynamic Dynamic Transition (Capacitor charge/discharge) Transition (Capacitor charge/discharge) Short-circuit Short-circuit Static Static Leakage Leakage P total =P dyn + P stat =P tran + P sc + P stat

9 Damu, 2008EGE535 Fall 08, Lecture 59 Short Circuit Power per Transition: P sc i sc (t) v i (t) V DD C R on v o (t)

10 Damu, 2008EGE535 Fall 08, Lecture 510 Short Circuit Current, i sc (t) n-transistor starts conducting Time (ns) 0 I sc V DD 0 V DD - V Tp V Tn t1t1 t3t3 i sc (t) V i (t) V o (t) p -transistor cuts-off I scmax i sc (t) vi vi V DD R on vo vo VTVT t2t2

11 Damu, 2008EGE535 Fall 08, Lecture 511Approximations Time V DD 0 V DD - V Tp V Tn V i (t)VTVT 0.1 0.9 rr  =  r =  f V i (0) = 0, V i (t) Linear rise V i (t)= 0.8V DD t / V i (t)= 0.8V DD t / 

12 Damu, 2008EGE535 Fall 08, Lecture 512 Short Circuit Current, i sc (t) More Assumptions: Symmetrical Inverter  n =  p, V tn = -V tp I = i peak @ V i (t) = V Th V Th =V DD /2 I d = (  /2)(V i (t) – V tn ) 2 0  I  i max ∫ t1 t 2 dt I avg = 2(2/T) ∫ t1 t 2 (  /2)(V i (t) – V tn ) 2 dt V i (t) = 0.8V DD t / V i (t) = 0.8V DD t /  V i (t 1 ) = V tn = 0.8V DD t 1 / , t 1 =  V tn /0.8V DD V i (t 2 ) = V DD /2 = 0.8V DD t 2 / , t 2 =  /1.6 0 I sc V DD 0 V DD - V Tp V Tn t1t1 t3t3 i sc (t) V o (t) I scmax V Th t2t2 V i (t) 

13 Damu, 2008EGE535 Fall 08, Lecture 513 Short Circuit Current, i sc (t) ∫ t1 t 2 dt I avg = (2  /T) ∫ t1 t 2 (0.8V DD t/  – V tn ) 2 dt Integrating and Simplifying I avg = I avg =   (V DD – 2V tn ) 3 /9.6TV DD P short (Avg) = V DD I avg =   (V DD – 2V tn ) 3 /9.6T 0 I sc V DD 0 V DD - V Tp V Tn t1t1 t3t3 i sc (t) V o (t) I scmax V Th t2t2 V i (t) 

14 Damu, 2008EGE535 Fall 08, Lecture 514 Peak Short Circuit Current Increases with the size (or gain, β) of transistors Increases with the size (or gain, β) of transistors Decreases with load capacitance, C L Decreases with load capacitance, C L Largest when C L = 0 Largest when C L = 0 Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp. 147-166. Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp. 147-166.

15 Damu, 2008EGE535 Fall 08, Lecture 515 Approximate Short-Circuit Energy E sc =∫ t1 t3 V DD i sc (t)dt, E sc =∫ t1 t3 V DD i sc (t)dt, Assuming Triangular I SC Assuming Triangular I SC E sc = (t 3 – t 1 ) I scmax V DD / 2 E sc = (t 3 – t 1 ) I scmax V DD / 2 E scf = t f V DD I scmax / 2 E scf = t f V DD I scmax / 2 E scr = t r V DD I scmaxr / 2 E scr = t r V DD I scmaxr / 2 E scf = E scr = 0, when V DD = |V Tp | + V Tn E scf = E scr = 0, when V DD = |V Tp | + V Tn 0 I sc V DD 0 V DD - V Tp V Tn t1t1 t3t3 i sc (t) V o (t) I scmax V Th t2t2 V i (t) 

16 Damu, 2008EGE535 Fall 08, Lecture 516 Impact of C L on Short Circuit Current

17 Damu, 2008EGE535 Fall 08, Lecture 517 Short-Circuit Energy Increases with rise and fall times of input Increases with rise and fall times of input Decreases for larger output load capacitance Decreases for larger output load capacitance Decreases and eventually becomes zero when V DD is scaled down Decreases and eventually becomes zero when V DD is scaled down

18 Damu, 2008EGE535 Fall 08, Lecture 518 Short Circuit Power P sc =α f ck E sc

19 Damu, 2008EGE535 Fall 08, Lecture 519 P sc, Rise Time and Capacitance V DD CLCL R on R = large v i (t) v o (t) i c (t)+i sc (t) tftf trtr v o (t) ─── R↑ v o (t) V DD

20 Damu, 2008EGE535 Fall 08, Lecture 520 i sc, Rise Time and Capacitance -t V DD [ 1- exp ( ───── )] v o (t) R↓(t) C I sc (t) =──── =────────────── R↑(t)

21 Damu, 2008EGE535 Fall 08, Lecture 521 Short-circuit Current with Load input slope 500 psec For small load capacitance, power is dominated by I Peak Short circuit power is minimized by matching the rise/fall times of the input and output signals – slope engineering.

22 Damu, 2008EGE535 Fall 08, Lecture 522 P sc, Rise Times, Capacitance For given input rise and fall times short circuit power decreases as output capacitance increases. For given input rise and fall times short circuit power decreases as output capacitance increases. Short circuit power increases with increase of input rise and fall times. Short circuit power increases with increase of input rise and fall times. Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times. Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times.

23 Damu, 2008EGE535 Fall 08, Lecture 523 Summary: Short-Circuit Power Short-circuit power is consumed during each transition (increases with input transition time). Short-circuit power is consumed during each transition (increases with input transition time). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Increasing the output load capacitance reduces short-circuit power. Increasing the output load capacitance reduces short-circuit power. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when V DD ≤ |V tp | + V tn. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when V DD ≤ |V tp | + V tn.

24 Damu, 2008EGE535 Fall 08, Lecture 524 i scmax, Rise Time and Capacitance Small C Large C tftf 1 ──── R↑(t) i scmax v o (t) i t

25 Damu, 2008EGE535 Fall 08, Lecture 525 Pass Transistor Combinational Logic Circuits

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