1. Digital LLRF plans at the Australian Synchrotron P.Corlett, K.Zingre, G. LeBlanc Australian Synchrotron, 800 Blackburn Road, Clayton 3168, Victoria, Australia email: peter.corlett@synchrotron.org.au Existing LLRF systems LINAC The linac LLRF system consists of a pulsed RF amplifier from SSB Electronic. This unit is no longer available or supported. This is a major issue as the system contains programmable elements which source code is not available. Due to the short pulse length (~4us), fast feedback control is not possible, and therefore the Linac operates in open loop pulsed mode. RF phase and amplitude is controlled manually and no pulse to pulse feedback exists. Problems have been experienced with amplitude stability. BOOSTER The booster LLRF system was supplied as a complete system by ACCEL (now Research Instruments) and is a combination of an analogue RF controller and a digital National Instruments PXI system. The PXI system provides an interface with EPICS, provides ADC and DAC channels for the analogue part of the control system, and generates the ramped setpoint waveforms. The analogue LLRF system consists of an IQ demodulator, followed by a pair of PI loops acting upon I and Q, followed by an IQ modulator. This system performs well, but system integration is excessively complex and confusing. STORAGE RING The complete storage ring RF (SRRF) system was provided by Toshiba and has so far performed to an acceptable level. Toshiba integrated a traditional analogue LLRF system from Thamway. Thamway’s design stems from the early days of the KEK in the 1980s and many of the components within the LLRF system have become obsolete. The system is also labour intensive to maintain, limited in dynamic range, functionality and diagnostics. Frequent LLRF Instability issues and beam loss caused by minor mains variation on the other hand have been mitigated after installation of a site UPS. Storage ring LLRF system controller Prototype A demonstration system to perform digital LLRF tasks is being prepared. This will be based upon the LLRF4.6 board developed by Larry Doolittle of LBNL and Dmitry Teytelman of Dimtel. [4] Hardware The LLRF4.6 is based around the Xilinx Spartan 6 FPGA, and has 4 high speed 14 bit ADCs, 2 x 14 bit DACs, along with slow speed DAC and ADC resources. Communication to a host computer is achieved through a USB2 connection facilitated by a Cypress FX2 USB2 chip. A major advantage of the LLRF4.6 evaluation board over the majority of commercially available evaluation boards, is the integrated analogue downcoversion / upconversion circuitry, which reduces the requirement for separate analogue front ends. RF components for the front ends can be selected to match RF frequencies up to 3GHz. The LLRF4.6 will be integrated into a robust chassis for installation, and will use a linux PC as a host for communication with the LLRF4.6. This PC will also run an EPICS IOC to allow high level control system access to registers and memory in the FPGA. LLRF4 evaluation board Laboratory bench test setup FPGA / USB Firmware FPGA firmware is being developed in house within the Xilinx ISE development environment using a combination of Verilog and Xilinx IP Core-gen components. For USB communication with the host computer, FPGALink is being used [5]. FPGALink is an open source end to end solution, implementing JTAG configuration of the FPGA through the Cypress FX2 chip, and also providing a straightforward API (in multiple programming languages) for post configuration communication between the host computer and the FPGA. Communication is implemented as 127 individual addressable FIFO channels, where each FIFO can be of any length. Current Progress At this stage, end to end (FPGA to EPICS IOC & GUI) code has been written to allow access to the ADC and DAC channels, along with various critical components in the DSP chain such as Non- IQ demodulator, IQ modulator, memory blocks, channel filtering and PI controller. In the coming months this will be developed to a full featured LLRF prototype for evaluation. EPICS EDM GUI under development Opportunities Linac Due to the short RF pulse length of the linac, traditional PID feedback during the pulse is not feasible. The major benefit that could be obtained by a modern digital LLRF system is in measuring waveforms of phase and amplitude during the pulse. Pulse to pulse phase and amplitude feedback is also an interesting possibility. A planned upgrade to the Linac involves the installation of a SLED cavity system to allow operation with only 1 klystron rather than 2 providing increased redundancy [3]. The RF waveforms generated by the SLED cavity will be complex, involving rapid changes of both amplitude and phase. The SLED cavity will also require the input RF pulse to have a 180 degree phase flip, which could be implemented by a digital controller. SLED cavity Drive waveforms SLED cavity output waveforms Booster / Storage ring Due to the aging of the storage ring RF system and the Booster, a long term objective exists to replace both of these LLRF systems with a standardised digital LLRF system based upon FPGA technology. As the booster and the storage ring are both 500MHz systems, it makes sense to replace both with a common platform. In all cases, enhanced diagnostic capabilities is a strong driver for adopting digital systems. Abstract The Australian Synchrotron is a third generation 3GeV, 200mA light source located in Melbourne, and has been in operation since 2007. Three major RF systems form part of the machine to power the accelerator structures. Two 3 GHz 35 MW pulsed klystrons and two 500 MHz 500W amplifiers power the LINAC accelerating structures and gun [1]. A 500 MHz 60 kW IOT amplifier powers a normal conducting 5 cell cavity operating in a 1 second ramp in the booster ring [1]. The storage ring RF system consists of four 500 MHz normal conducting cavities, each powered by a 150 kW CW klystron amplifier [2]. In each case, Low level RF control is achieved using analogue methods and each LLRF system is from a different vendor. These systems have performed well so far under stable conditions, however have exhibited instability under transient conditions, thermal drift and EMC related issues. For this reason, coupled with ageing, obsolete components, running costs and limited diagnostics, plans are being prepared for a phased replacement of LLRF systems with a modern FPGA based control system. A description of the existing system is presented along with initial plans for implementing a standardised FPGA based digital control system. Conclusion / Future work Once a prototype LLRF system has been produced and demonstrated, a decision will be made on whether to extend the prototype into full production and integrate it into the machine, or take a different approach. Simultaneously, commercially available systems will be evaluated, to establish the best route to take. This evaluation will include technical performance, cost and risk. In either case, skills in digital LLRF systems are being developed at the Australian Synchrotron to allow ongoing development and support to future LLRF projects. The first deployment anticipated for the new digital LLRF system is anticipated to be in making phase and amplitude waveform measurements of the waveguide power in the Linac. Therefore the RF front ends are being populated with RF components suitable for 3GHz operation. FPGA firmware and host software is being kept as generic as possible to allow the 3Ghz system to be readily adapted for 500MHz operation References [1] C.Piel et al, “Commissioning of the Australian Synchrotron Injector RF systems”, EPAC’06 Edinburgh, UK 2006 [2] S.Takama et al, “Completion of the Australian Synchrotron Storage Ring RF system commissioning” PAC’07 Albuquerque, USA 2007 [3] K.Zingre et al, “Proposed Linac upgrade with a SLED cavity at the Australian Synchrotron”, IPAC’15, Richmond USA 2015 [4] D.Teytelman, “LLRF4.6 Technical Information”, http://www.dimtel.com/support/llrf4/index [5] C.McClelland “FPGAlink repository”, https://github.com/makestuff/