1. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE 30kA Energy Extraction Semi-Conductor Switch PRR: 29-02-2016 SM18 - CLUSTER D Software and signal conditioning Mateusz Bednarek TE-MPE-EE 1

2. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Outline Requirements for the control system Choice of components Architecture overview Data buffers for switch diagnostics Algorithms’ overview Selected implementation details Signal conditioning Further work 2

3. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Tasks of the controller Monitoring of 32 analogue channels @ 100 kS/s and triggering appropriate actions Monitoring of 16-24 DIO and triggering appropriate actions Controlling 8-16 DIO to achieve required actions In case of a trigger (internal or external) recording of post- mortem (PM) buffer with all AIN, DIO, internal variables Monitoring of the slow evolution of each signal with a high precision and storage in the logging database Not meant to replace fast scopes during the prototype study 3

4. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Controller The controller is based on NI cRIO-9030 o 1 GB RAM o 2 cores Intel Atom @1.33 GHz o 4 slots NI-9403 - 32 x Digital IO @ 140 kHz 2 x NI-9220 – 2 x 16 x 16 bit analog IN @ 100 kS/s NI-9214 – 16 x thermocouple @68 S/s o Powered from two redundant 24 V power supplies 4

5. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Real Time system FPGA PM Logging Analog Digital SM18 PLC: PC, QPS etc. cRIO PM Technical network Simplified overview Configuration settings Power electronics analog signal conditioning & low level control electronics 1 n 5

6. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE FPGA and RT target roles FPGA: Data acquisition Data pre-processing Sending data to the RT target Simple and fast fault detection Simple data interpretation RT target: Reception of pre-processed data from the FPGA Floating point maths Advanced fault detection Data interpretation Communication with the external world o Status o Sending logging data o Sending PM data o Reception of software requests Configuration storage 6

7. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE cRIO resources at the moment Compilation completed successfully. Device Utilization --------------------------- Slice Registers: 51.0% (41853 out of 82000) Slice LUTs: 78.6% (32232 out of 41000) Block RAMs: 28.9% (39 out of 135) DSP48s: 7.9% (19 out of 240) Timing --------------------------- 40 MHz Onboard Clock: 40.00 MHz (Met MHz maximum) 80MHz: 80.00 MHz (Met MHz maximum) Compilation Time --------------------------- Date submitted: 16/02/2016 18:48 Date results were retrieved: 16/02/2016 19:37 Time waiting in queue: 00:25 Time compiling: 48:55 - Generate Xilinx IP: 00:00 - Synthesize - Vivado: 26:01 - Optimize Logic: 02:55 - Place: 09:37 - Optimize Timing: 00:24 - Route: 07:33 - Generate Programming File: 02:11 Can be optimised by using an external compile farm It is still being optimised FPGA compilation: Most of the functionalities are already covered 7

8. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Fault detection Basic fault detection is implemented on FPGA – simple threshold and discrimination time evaluation Floating point calculations are done on RT and results are fed back to the FPGA (so far only for thermocouples) o Significant time lag in contrast with a solution implemented directly on the FPGA Types of interlocks o FPA faults  All temperatures: lower and upper limit  All voltages: lower and upper limit  Selected digital states are interpreted as faults  Selected internal software errors are interpreted as faults o SPA faults  No such scenario at the moment o Power permit faults  No such scenario at the moment o External FPA request  Not a fault (Normal operation from EE point of view) The fault matrix needs to be officially released. The fault scenarios need to be studied including time budgets. 8

9. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE PM data Displayed locally if the screen is present Displayed in the expert application available in the technical network Stored in a binary file locally o There is an option not to store the file locally (flash memory with a limited number of cycles) o Recallable using the expert application in the technical network To be implemented: Sending to the CERN PM central storage Technical details: Full bandwidth is stored +-10 V range of the 16 bit ADC -> resolution 305 uV Analog signals: 1 s buffer, trigger location adjustable Temperatures: 4 s buffer, trigger location adjustable Digital signals: 2 s buffer, trigger location adjustable Entire binary PM file takes 25 MB: longer buffers can be envisaged Names can be easily assigned via a configuration file Technical details: Full bandwidth is stored +-10 V range of the 16 bit ADC -> resolution 305 uV Analog signals: 1 s buffer, trigger location adjustable Temperatures: 4 s buffer, trigger location adjustable Digital signals: 2 s buffer, trigger location adjustable Entire binary PM file takes 25 MB: longer buffers can be envisaged Names can be easily assigned via a configuration file SM18 operation Prototype tests 9

10. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Logging data Status, not time critical Displayed locally if screen connected Displayed in the expert application available on the technical network o Possibility to store the data for long term trend analysis To be implemented: Sending to the central CERN logging database SM18 operation Prototype tests Technical details: Full bandwidth is used for analogue input signals o Averaging of 40 kS o One point every 400 ms (refresh rate of the status loop) o Increased accuracy vs raw signals o On +-10 V range the usable resolution is at the level of 20-50 uV Names can be easily assigned via a configuration file Technical details: Full bandwidth is used for analogue input signals o Averaging of 40 kS o One point every 400 ms (refresh rate of the status loop) o Increased accuracy vs raw signals o On +-10 V range the usable resolution is at the level of 20-50 uV Names can be easily assigned via a configuration file 10

11. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE FPGA operation simplified INIT RT: Floating point calculations INIT SyncSync FPGA RT start ∑ FPA faults Record PM and STOP External FPA request Send PM and STOP Set IO bits ∑ SPA faults ∑ Warnings Transfer status to RT AIN: Acquisition Fault detection Transfer to RT Average DIO: Acquisition Fault detection Transfer to RT TT: Acquisition Transfer to RT Ext. watchdog reset DMA 11

12. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE RT simplified INIT SyncSync FPGA RT start Record PM and STOP Generate PM Send PM STOP UI: Gather the status data from the FPGA Maintain a circular buffer and display the data Publish the data for the expert app Collect requests and send to the FPGA Data acquisition & Scan for faults start Logging: Send data to the logging DB IF FAULT DMA data receive: Maintain PM buffers o AIN o DIO o TT o Local variables Floating point calculations Advanced conditions evaluation cRIO internal watchdog DMA 12

13. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Configuration files Configuration files are stored locally on RT target At the start-up they are read out and transmitted to the FPGA Content: o Basic time intervals o PM recording settings o Names and units of measured signals o Calibration factors: offsets and gains o Fault detection thresholds Format: o.csv file for analogue signals o.csv file for digital signals o.ini text file for other values 13

14. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Watchdog Two watchdogs are implemented in the software: cRIO internal watchdog o If the RT main loop hangs, the cRIO internal watchdog circuitry will power-cycle the controller o Timeout 100 ms External watchdog o If the FPGA hangs, the external watchdog will issue an interlock which will open the FPA loop o To be included in the new version of control electronics o The reset signal is already implemented o Timeout: about 10 ms 14

15. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE GUI (1/3) 15

16. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE GUI (2/3) 16

17. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE GUI (3/3) 17

18. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Signal conditioning Galvanic isolation from the life part cRIO inputs get only +/- 10 V o Shunt -> gain of 10 with PGA204AU + AD215AY (isolation amplifier) o LEM -> signal transmitted directly o Vce -> voltage divider 166:1 + gain of 1 with PGA204AU + AD215AY o 24 V power -> voltage divider 3:1 Necessity for calibration of each channel: offset + slope Is it better to go for another solution: Verivolt? 18

19. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Further work Calibration of the measurement chain Tests of all interlocked mechanisms  Interlock test procedure  Interlock tester – simulator box Fine tuning of fault criteria Fine tuning of the UI Finalizing of the signal conditioning circuitry Implementation of features needed for SM18 operation 19

20. Any questions? 20

21. Annex 21

22. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE List of digital signals RT_FIFO_err RT_FPA_AIN RT_stop_acq RT_FPA_TT_float RT_FPGA_init_err RT_Params_sent_OK RT_FPA_request RT_Config_file_err RT_FPA RT_FPA_DIO RT_Open_switch_cmd Host_FPA_request RT_running RT_finished_late_local_var RT_Host_close_cmd RT_close_cmd RT_loop_open RT_SPA RT_local_mode FPGA_FPA_DIO FPGA_FPA_AIN FPGA_FPA_request_TT FPGA_FPA_request FPGA_ovfl_TT FPGA_ovfl_AIN FPGA_ovfl_digital FPGA_Close_command FPGA_close_cmd_received FPGA_Loop_open FPGA_Local_mode FPGA_open_sw_command FPGA_start-up FPGA_generate_PM FPGA_SPA_sum_faults FPGA_FPA_sum_faults Fault_detected_by_cRIO FPGA_AIN_0-15_trip FPGA_AIN_16-31_trip FPGA_LEM_sharing_trip FPGA_shunt_sharing_trip FPGA_shunt_LEM_unbalanced Close-cmd RL1_L-cmd RL1_R-cmd Rem-reset-cmd LEDopen-cmd LEDclose-cmd PLC_warning Power_permit FPA-stat PLC-stat OpenPB-stat ClosePB-stat LocResetPB-stat LocalSwitch-stat RemoteSwitch-stat DIO_15 Eletta_Heatsink_3 Eletta_Heatsink_2 Eletta_Emitter-busbar Eletta_Heatsink_4 Eletta_Collector-busbar Spare_interlock Eletta_Laminated_busbar Eletta_Heatsink_1_master DIO_24 … DIO_30 heartbeat DIO: Internal FPGA: Internal RT: 22

23. 30kA IGBT EE switch PRR 29/02/2016, Mateusz Bednarek, TE/MPE-EE Configuration file: AIN Ch nameUnitUpper limitLower limit Discrimination time [us or ms]MultiplierOffset LEM_1A2000-30010002000.00225 LEM_2A2000-3001000200-0.01025 LEM_3A2000-3001000200-0.011 LEM_4A2000-3001000200-0.0017 5V16-16100010.017 6V16-16100010.017 7V16-16100010.017 8V16-16100010.017 U_24_V_LV2620100030 U_24_V_RV2620100030 11V16-16100010.017 12V16-16100010.017 13V16-16100010.017 14V16-16100010.017 15V16-16100010.017 16V -16100010.017 Shunt_1A2000-30010003333.330.01821 V_CE_1V1600-160010001660.0196 Shunt_2A2000-30010003333.330.02166 V_CE_2V1600-160010001660.0176 Shunt_3A2000-30010003333.330.01634 V_CE_3V1600-160010001660.018205 Shunt_4A2000-30010003333.330.017735 V_CE_4V1600-160010001660.02513 … 23