1. Computer Architecture: A Constructive Approach Implementing SMIPS Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology January 12, 2012L4-1 http://csg.csail.mit.edu/SNU

2. The SMIPS ISA  Processor State  32 32-bit GPRs, R0 always contains a 0  PC, the program counter  some other special registers  Data types  8-bit byte, 16-bit half word  32-bit word for integers  Load/Store style instruction set  data addressing modes- immediate & indexed  branch addressing modes- PC relative & register indirect  Byte addressable memory- big endian mode  All instructions are 32 bits January 12, 2012 L4-2http://csg.csail.mit.edu/SNU

3. Instruction Execution  Execution of an instruction involves  1. Instruction fetch  2. Decode  3. Register fetch  4. ALU operation  5. Memory operation (optional)  6. Write back  and the computation of the address of the  next instruction January 12, 2012 L4-3http://csg.csail.mit.edu/SNU

4. Implementing an ISA Instructions fetch requires an Instruction memory, PC Decode requires understanding the instruction format Register Fetch requires interaction with a register file with a specific number of read/write ports ALU must have the ability to carry out the specified ops Memory operations requires a data memory Write-back requires interaction with the register file January 12, 2012 L4-4http://csg.csail.mit.edu/SNU

5. Instruction formats Only three formats but the fields are used differently by different types of instructions 6 5 5 16 opcode rsrt immediate I-type 6 5 5 5 5 6 opcode rsrt rd shamt func R-type 6 26 opcode target J-type January 12, 2012 L4-5http://csg.csail.mit.edu/SNU

6. Instruction formats cont Computational Instructions Load/Store Instructions opcode rsrt immediate rt  (rs) op immediate 6 5 5 5 5 6 0 rsrt rd 0 func rd  (rs) func (rt) rs is the base register rt is the destination of a Load or the source for a Store 6 55 16 addressing mode opcode rsrt displacement (rs) + displacement 31 26 25 21 20 16 15 0 January 12, 2012 L4-6http://csg.csail.mit.edu/SNU

7. Control Instructions Conditional (on GPR) PC-relative branch target address = (offset in words)4 + (PC+4) range: 128 KB range Unconditional register-indirect jumps Unconditional absolute jumps target address = {PC, target4} range : 256 MB range 6 55 16 opcode rs offset BEQZ, BNEZ 6 26 opcode target J, JAL 6 55 16 opcode rs JR, JALR jump-&-link stores PC+4 into the link register (R31) January 12, 2012 L4-7http://csg.csail.mit.edu/SNU

8. A single-cycle implementation A single-cycle MIPS implementation requires: A register file with 2 read ports and a write port An instruction memory, separate from data memory so that we can fetch an instruction as well as perform a data operation (Load/store) on the memory fetch & execute pc iMemdMem rf CPU January 12, 2012 L4-8http://csg.csail.mit.edu/SNU

9. but first a digression on types … January 12, 2012L4-9 http://csg.csail.mit.edu/SNU

10. Example: Complex Addition typedef struct{ Int#(t) r; Int#(t) i; } Complex#(numeric type t) deriving (Eq,Bits); function Complex#(t) \+ (Complex#(t) x, Complex#(t) y); Int#(t) real = x.r + y.r; Int#(t) imag = x.i + y.i; return(Complex{r:real, i:imag}); endfunction What is the type of this + ? January 12, 2012 L4-10http://csg.csail.mit.edu/SNU

11. Example: A 4-Instruction ISA typedef enum {R0;R1;R2;…;R31} RName; typedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName valueR; RName addrR;} Store } Instr deriving(Bits, Eq); typedef Bit#(32) Iaddress; typedef Bit#(32) Daddress; typedef Bit#(32) Value; January 12, 2012 L4-11http://csg.csail.mit.edu/SNU

12. Deriving Bits To store datatypes in register, fifo, etc. we need to know how to represent them as bits (pack) and interpret their bit representation (unpack) Deriving annotation automatically generates the “pack” and “unpack” operations on the type (simple concatenation of bit representations of components) typedef struct { … } Foo deriving (Bits); January 12, 2012 L4-12http://csg.csail.mit.edu/SNU

13. Tagged Unions: B it Representation 00 dst src1 src2 01 condR addrR 10 dst addrR 11 dst imm typedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName dst; Immediate imm;} AddImm; } Instr deriving(Bits, Eq); Automatically derived representation; can be customized by the user written pack and unpack functions January 12, 2012 L4-13http://csg.csail.mit.edu/SNU

14. Pattern-matching: A convenient way to extract datastructure components The &&& is a conjunction, and allows pattern-variables to come into scope from left to right case (m) matches tagged Invalid : return 0; tagged Valid.x : return x; endcase if (m matches (Valid.x) &&& (x > 10)) typedef union tagged { void Invalid; t Valid; } Maybe#(type t); x will get bound to the appropriate part of m January 12, 2012 L4-14http://csg.csail.mit.edu/SNU

15. now back to SMIPS … January 12, 2012L4-15 http://csg.csail.mit.edu/SNU

16. Single-Cycle SMIPS PC Inst Memory Decode Register File Execute Data Memory +4 January 12, 2012 L4-16http://csg.csail.mit.edu/SNU Datapath is shown only for convenience; it will be derived automatically from the high- level textual description

17. Single-Cycle SMIPS code structure module mkProc(Proc); Reg#(Addr) pc <- mkRegU; RFile rf <- mkRFile; Memory mem <- mkMemory; rule fetchExecute; //fetch let instResp <- mem.iside(MemReq{…}); //decode let decInst = decode(instResp); //execute let execInst = exec(decInst, pc, rVal1, rVal2); if(instType Ld || St) … mem.dside(MemReq{…}); pc <= execInst.brTaken ? execInst.addr : pc + 4; //writeback if(instType Alu || Ld) rf.wr(rDst,data); endrule endmodule; January 12, 2012 L4-17http://csg.csail.mit.edu/SNU

18. Type: Instr (partial definition) Captures the fields for each instruction  typedef union tagged { struct{Rindx rbase; Rindx rdst; Simm offset;} LW; struct{Rindx rbase; Rindx rsrc; Simm offset;} SW;  struct{Rindx rsrc; Rindx rdst; Simm imm;} ADDIU; struct{Rindx rsrc; Rindx rdst; Shamt shamt;} SLL; struct{Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; struct{Target target; } J; struct{Rindx rsrc; } JR; struct{Rindx rsrc; Rindx rdst; } JALR; struct{Rindx rsrc1; Rindx rsrc2; Simm offset;} BEQ; struct{Rindx rsrc; Simm offset; } BLEZ; void ILLEGAL; } Instr deriving(Eq); We need to define our own pack/unpack functions to match the MIPS instruction formats January 12, 2012 L4-18http://csg.csail.mit.edu/SNU

19. Miscellaneous type defs January 12, 2012 L4-19http://csg.csail.mit.edu/SNU typedef Bit#(5) Rindx; typedef Bit#(16) Simm; typedef Bit#(16) Zimm; typedef Bit#(5) Shamt; typedef Bit#(26) Target; typedef enum {Alu, Ld, St, Other} IType deriving(Bits, Eq); typedef enum {Eq, Neq, Le, Lt, Ge, Gt, J, JR, N} BrType deriving(Bits, Eq); typedef enum {Add, Sub, And, Or, Xor, Nor, Slt, Sltu, LShift, RShift, Sra} Func deriving(Bits, Eq);

20. pack for type Instr partial definition function Bit#(32) pack( Instr instr ); case ( instr ) matches tagged LW.it : return {opLW, it.rbase, it.rdst, it.offset}; tagged SW.it : return {opSW, it.rbase, it.rsrc, it.offset}; tagged ADDIU.it : return {opADDIU, it.rsrc, it.rdst, it.imm}; tagged SLL.it : return {opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL}; tagged J.it : return {opJ, it.target}; tagged BEQ.it : return {opBEQ, it.rsrc1, it.rsrc2, it.offset}; endcase endfunction Also need to define constants opLW, … January 12, 2012 L4-20http://csg.csail.mit.edu/SNU

21. unpack for type Instr partial definition function Instr unpack( Bit#(32) instrBits ); let opcode = instrBits[ 31 : 26 ]; let rs = instrBits[ 25 : 21 ]; let rt = instrBits[ 20 : 16 ]; let rd = instrBits[ 15 : 11 ]; let shamt = instrBits[ 10 : 6 ]; let funct = instrBits[ 5 : 0 ]; let imm = instrBits[ 15 : 0 ]; let target = instrBits[ 25 : 0 ]; case ( opcode ) opLW : return LW {rbase:rs, rdst:rt, offset:imm }; … default : return ILLEGAL; endcase endfunction January 12, 2012 L4-21http://csg.csail.mit.edu/SNU

22. unpack for type Instr partial definition case ( opcode ) opLW : return LW {rbase:rs, rdst:rt, offset:imm}; opADDIU : return ADDIU {rsrc:rs, rdst:rt, imm:imm}; opJ : return J {target:target }; opJAL : return JAL {target:target }; opFUNC : case ( funct ) fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; fcJR : return JR { rsrc:rs }; fcJALR : return JALR {rsrc:rs, rdst:rd}; default : return ILLEGAL; endcase default : return ILLEGAL; endcase January 12, 2012 L4-22http://csg.csail.mit.edu/SNU

23. Decoding Instructions: extracts fields needed for execution from each instruction decode inst branchComp rDst rSrc1 rSrc2 imm ext aluFunc instType 31:26 5:0 31:26 20:16 15:11 25:21 20:16 15:0 25:0 January 12, 2012 L4-23http://csg.csail.mit.edu/SNU Pure combinational logic: will be derived automatically from the high-level description

24. Decoding Instructions function DecodedInst decode(Bit#(32) inst, Addr pc); DecodedInst dInst = ?; let opcode = instrBits[ 31 : 26 ]; let rs = instrBits[ 25 : 21 ]; let rt = instrBits[ 20 : 16 ]; let rd = instrBits[ 15 : 11 ]; let shamt = instrBits[ 10 : 6 ]; let funct = instrBits[ 5 : 0 ]; let imm = instrBits[ 15 : 0 ]; let target = instrBits[ 25 : 0 ]; case (opcode)... endcase return dInst; endfunction January 12, 2012 L4-24http://csg.csail.mit.edu/SNU

25. Decoding Instructions: Load & Store case (opcode) LW, SW: begin dInst.instType = opcode==LW ? Ld : St; dInst.aluFunc = Add; dInst.rDst = rt dInst.rSrc1 = rs dInst.rSrc2 = rt dInst.imm = signExtned(imm); end … endcase January 12, 2012 L4-25http://csg.csail.mit.edu/SNU

26. Decoding Instructions: R-Type ALU case (opcode) … RAlu: begin dInst.instType = Alu; dInst.aluFunc = case (funct)... endcase; dInst.rDst = rd; dInst.rSrc1 = rs; dInst.rSrc2 = rt; end … endcase January 12, 2012 L4-26http://csg.csail.mit.edu/SNU

27. Decoding Instructions: I-Type ALU case (opcode) … IAlu: begin dInst.instType = Alu; dInst.aluFunc = case (funct)... endcase; dInst.rDst = rt; dInst.rSrc1 = rs; dInst.imm = opcode==SignedIAlu ? signExtend(imm): zeroExtend(imm); end … endcase January 12, 2012 L4-27http://csg.csail.mit.edu/SNU

28. Decoding Instructions: Jump case (opcode) … J, JAL: begin dInst.instType = opcode==J ? J : Jal; dInst.rDst = 31; dInst.imm = zeroExtend({target, 2’b00}); end rJump: begin dInst.instType = funct==JR ? Jr : Jalr; dInst.rDst = rd; dInst.rSrc1 = rs; end …. endcase January 12, 2012 L4-28http://csg.csail.mit.edu/SNU

29. Decoding Instructions: Branch case (opcode) … Branch: begin dInst.instType = Br; dInst.branchComp = case (opcode)... endcase; dInst.rSrc1 = rs; dInst.rSrc2 = rt; dInst.imm = signExtend({imm, 2’b00}); end … endcase January 12, 2012 L4-29http://csg.csail.mit.edu/SNU