1. PS02CINS02 Unit 1 Advanced Microprocessors

2. Comparison between 8085 and 8086 80858086 Size8-bit16-bit Address Bus and Memory16-bit/64kB20-bit/1MB Instruction QueueNO6 byte PipelineNO2 stage Multiprocessor supportNOYES IO25664K Co-Processor InterfaceNOYes ArithmaticsInteger and BCDInteger,BCD,ASCII Mul/DivNo instructionInstructions are there Speed3,5,6MHz5,8,10MHz External HWLess RequirementLarge ModesNormalMaximum & Minimum Addressing modes59 MemorySingle BlockSegmented Interrupts5HW & 8SW2HW & 256SW

3. Architecture of 8086 parallel processing processing units:  Bus Interface Unit (BIU)  Execution Unit (EU) both operate at the same time fetch and execution independent operations

4. 8086 Architecture BIU EU

5. Bus Interface Unit Facilitates comm. between the EU and the memory or I/O circuits. Perform bus operation such as inst. fetching, reading/writing of data for memory or i/o peripherals. Transmit address, data, and the control signals on the buses. Contains CS, DS, ES, SS and IP registers, address generation adder, bus control logic, and an instruction queue.

6. Bus Interface Unit An internal bus connects the EU and BIU. While the EU is executing an instruction the BIU fetches up to six bytes of next instruction in the instruction queue Perform instruction queuing and data acquisitions. 8-bit (16-bit) bi-directional data bus for 8088 (8086). 20-bit address bus Instruction queue to implement a pipelined architecture

7. Execution Unit Responsible for decoding and executing instruction. Contains: ALU, Flags, general purpose and temporary register. The EU has eight registers AX, BX, CX, DX, SI, DI, BP and SP. In addition EU has temporary registers for holding operands for CPU, and the FLAGS registers

8. Execution Unit EU accesses the instruction from the instruction queue and data from general-purpose register. It reads one instruction at a time, decodes it, generates operand address if necessary, passes them to BIU and requests to perform the read/write cycle to memory or I/O, and performs the operation specified by the instruction on operand. During execution, EU may test the flags and update these flags based on the results of execution.

9. Software Model IPCSDSSSESAXBXCXDXSPBPSIDISR Code Segment(64kB)Data Segment(64kB)Stack Segment(64kB)Extra Segment(64kB) Input / Output Map 00000 FFFFF FFFF OOOO 8086  P External Memory Address Space Input/ Output Address Space

10. Software Model Various Registers and their purposes, functional capability and limitations. External memory and I/O devices’ organization. Less likely to change with new generation

11. Data Organization 8086 supports 1 MB of external memory Individually located bytes from 00000H to FFFFFH Byte wise organization Can access byte, word or double word (little endian) Even and odd address boundaries Aligned word (starts from even add.) Aligned double word (starts from add. multiple of 4)

12. Data Organization

13. Data Types Sizes:  Byte(8 bits)  Word(16 bits)  Double Word(32 bits) Integer: Signed and Unsigned  -128 to +127  -32768 to +32767  -(2 31 ) to + (2 31 -1) BCD No.s:  Unpacked  Packed ASCII Codes: S7 bit data S15 bit data S31 bit data 8 bit 16 bit 32 bit O O O OBCD Digit O BCD Digit 1BCD Digit O ASCII CODE

14. Segment Registers CS Code Segment SS Stack Segment DS Data Segment ES Extra Segment 1 MB memory can not be accessed at a time 64kB partitions (Segments) Only 4 segments active  Code Segment (Program)  Data Segment (Data)  Stack Segment (Stack)  Extra Segment (Data) 16 bit segment registers form base address of each segment. User accessible

15. Memory Segmentation  Data Segment B  Code Segment E  Stack Segment H  Extra Segment J Each segment starts from a 16-byte boundary. e.g. 00000 H, 00010 H, 00020 H Can be contiguous, adjacent, disjoint or overlapping. Data: DS = B ABC Code: CS = E DEGF Stack: SS = H HI Extra: ES = J Jk

16. Dedicated, Reserved & General use Memory FFFFFH Reserved FFFFBH Dedicated FFFF0H 0007FH Reserved 00013H Dedicated 00000H 8086 Memory Address Space (00000 H to FFFFF H ) 00000 H to 00013 H Dedicated Memory  For internal interrupts and exceptions (5x4) 00014 H to 0007F H Reserved Memory  For user defined interrupts(27x4) FFFFC H to FFFFF H Reserved Memory  For use with future products FFFF0 H to FFFFB H Dedicated Memory  Storage of HW reset JUMP  FFFF0 H is the RESET location

17. 8086 Registers 16 bit Identifies offset address of next instruction CS:IP= 20-bit physical address Normally increments in step of 2 Instruction Pointer Identifies offset address of top of STACK SS:SP= 20-bit physical address Stack Pointers For data access in Stack segment Used with base addressing mode Used to pass argument to subroutine Base Pointer SI and DI Used with DS and ES as offset for data Used with indexed addressing mode Used for string operations Index Registers

18. Data Registers AX: Word Multiply, Divide, I/O AL: Byte Multiply, Divide, I/O, Translate, BCD Arithmatic AH: Byte Multiply, Divide A BX: Translate B CX: String Operations, Loops as counter CL: Variable shift and rotate C DX: Word Multiply, Divide, Indirect I/O D

19. Status Register Carry Flag: set if carry out or borrow in for MSB of result CF Parity Flag: sit if the result has even parity PF Auxiliary Carry: set if carry out or borrow in at bit D3 for 8 bit operation or at bit D7 for 16 bit operation AF Zero Flag: set if the result of the last instruction is Zero ZF Sign Flag: MSB of the Result SF Over Flow Flag: Set if the signed operation result is out of range OF XXXX DFIFTFSFZFXAFXPFXCF

20. Status Register Trap Flag: If set the 8086 goes into single step mode Used for debugging the program TF Interrupt Flag: If set enables maskable HW interrupts. If reset the interrupts at INT pin will be ignored IF Direction Flag: Used for string operations If set the string instructions decrements address DF XXXXOFDFIFTFSFZFXAFXPFXCF

21. Memory Address Generation 0000 16-bit Segment Address16-bit Logical Address20-bit Physical Address Effective Address (IP) Segment Address (CS)

22. Stack Within memory map Used for temporary storage of data/address  CALL, PUSH, POP, RET Organized as words (32k words) At startup SP=FFFE H making  Stack bottom SS:FFFE H  Top of stack: SS:SP  End of stack: SS:0000 H Data transferred word wide Stack decrements by 2 and stores a word (PUSH) Multiple stacks allowed with only one active at a time SS SP Stack Segment SS:FFFE Stack Bottom SS: SPStack TopSS:0000Stack End

23. Input / Output Address Space Separate memory and IO space. Range: 0000 H to FFFF H Byte wide Page 0: 0000 H to 00FF H  (Specific instructions) Reserved: 00F8 H to 00FF H Input / Output Map FFFF OOOO Input/ Output Address Space

24. Addressing modes Way of locating data or operand An instruction may belong to one or more addressing modes or to neither of the modes.  Depending on data types used in instruction  Depending on memory addressing modes Describes type of operand and way to access it for instruction execution

25. Instruction types Sequential control flow  After execution of instruction passes control to next instruction  e.g. arithmatic, logical, data transfer and processor control instructions. Control transfer  After execution of instruction passes control to some predefined address or address specified in the instruction  e.g. branch instructions, JUMP, CALL, RET, INT etc.

26. Addressing modes for sequential control transfer Instructions Immediate  Immediate data/operand is part of instruction, appearing on successive byte/bytes  e.g. MOV AX,9080H,MOV BL,7FH Direct  A 16-bit address(offset) is provided as a part of instruction  e.g. MOV AX,[1080H],MOV BL,[127FH]  Here data resides in data segment, therefore, the effective address for the instructions are ((DS)x10H) + 1080H and ((DS)x10H) + 127FH respectively.

27. Addressing modes for sequential control transfer Instructions Register  In this type of operation operand is stored in register and referred to by register name  All registers except IP can be used.  e.g. MOV AX,BX,MOV BL,AH Register Indirect  In this mode the registers are holding the address of operand. Using address from register content the operand is accessed indirectly.  Registers BX, DI or SI can be used with DS or ES.  Default segment is DS  e.g. MOV AX,[BX],MOV CL,[BX]  Here data resides in data segment, therefore, the effective address for the instructions are ((DS)x10H) + BX and ((DS)x10H)+BX respectively.

28. Addressing modes for sequential control transfer Instructions Indexed  In this mode the index registers are holding the address of operand. In case of string instructions DS and ES are default segments for DI and SI respectively  Default segment is DS  e.g. MOV AX,[SI],MOV [DI],CL  Here data resides in data segment, therefore, the effective address for the instructions are ((DS)x10H) + SI and ((DS)x10H)+DI respectively. Register Relative  In this type of operation operand address is formed by adding 8- bit or 16-bit offset with the content of any of the registers BX, BP, SI and DI in default (DS or ES) segment.  e.g. MOV AX,50H[BX],MOVAH,1234H[DI]  Effective addresses are ((DS)x10H) + BX + 50H and ((DS)x10H)+DI + 1234H respectively.

29. Addressing modes for sequential control transfer Instructions Base Indexed  In this mode the address of operand is formed by addition of content of a base register (BX/BP) to the content of index register (SI/DI). In case of such instructions DS and ES are default segments.  e.g. MOV AX,[BX][SI]  The effective address for the instruction is ((DS)x10H) + BX+SI Relative Base Indexed  The effective address is formed by adding 8-bit or 16-bit displacement with sum of content of a base register (BX/BP) and an index register (SI/DI).  e.g. MOV AX,50H[BX][SI]  Effective addresses are ((DS)x10H) + BX + SI +50H.

30. Addressing modes for control transfer Instructions Intra-segment & Inter-segment Method of passing destination address to processor Modes for control transfer instructions Intersegment Intersegment directIntersegment indirect Intrasegment Intrasegment indirectIntrasegment direct

31. Addressing modes for control transfer Instructions Intra-segment Direct  Destination lies in the same segment as the instruction lies.  Immediate displacement value is defined in the instruction  The displacement is calculated relative to the IP.  Effective address = CS:(IP+8/16 bit displacement)  8-bit displacement= short jump  JMP SHORT LABEL  16-bit displacement= long jump  JMP NEAR PTR LABEL Intra-segment Indirect  Here the displacement is passed indirectly by either a register or memory location  JMP[BX]  JMP[BX + 2340H]

32. Addressing modes for control transfer Instructions Inter-segment Direct  Destination is in the different segment.  New segment as well as Immediate displacement value is defined in the instruction  JMP 5555H:2222H  Jump to effective address 2222H in segment 5555H Inter-segment Indirect  Here the displacement is passed indirectly by either a register or memory location  JMP[2000]  It seeks 2 consecutive words from the location defined in the DS and that becomes new CS and IP respectively.