1. Exploring the Rogue Wave Phenomenon in 3D Power Distribution Networks Xiang Hu 1, Peng Du 2, Chung-Kuan Cheng 2 1 ECE Dept., 2 CSE Dept. University of California, San Diego 10/25/2010

2. Page  2 Agenda  Introduction  System-level 3D PDN analysis  Chip-level 3D PDN analysis –Detailed 3D power grid model –Frequency-domain analysis –Time-domain analysis  Conclusions

3. Page  3 Introduction  Power delivery issues in 3D ICs –Total currents flowing through off-chip components increase with the number of stacked tiers –3D-related components (i.e., TSV, µbump) add more impedance to on-chip power grids  Previous power grid models for on-chip noise analysis are relatively simple –Missed detailed metal layer information –Not suitable for 3D PDN analysis  Detailed 3D PDN analysis has not been done –Frequency domain: resonance behavior –Time domain: worst-case noise

4. Page  4 System-Level 3D PDN model  Power delivery system including VRM, board and package  Multiple input current sources Z ext

5. Page  5 Impedance Profiles in System-Level 3D PDN Model  Common resonant peaks at VRM-board, board-package, and package-T1 interfaces.  No high-frequency peak for Z 11.  High-frequency peak for Z 22 due to T1-T2 resonance.  Small high-frequency bumps for Z 12 and Z 21 due to T1-T2 resonance. VRM-brd brd-pkg pkg-T1 T1-T2

6. Page  6 Chip-Level 3D Power Grid Model  Power grid –structure: M1, M3, M7, RDL –Extracted in Q3D  TSV: RLC model  Package: distributed RLC model

7. Page  7 2D PDN3D PDN Package inductance (L p )52.5pH Total on-chip cap (C c )7.92nF 246.9MHz Current Source @ T1, Output Voltage @ T1  Measured on-chip impedance on device layer, i.e., M1  2D PDN –Large impedance at low frequencies due to high resistive M1 –Only one resonance peak at package-die interface  3D PDN –Small impedance at low frequencies due to low resistive RDL on T2 –Mid-frequency resonance peak at package-die interface –Large high-frequency resonance peak around T2T location 2D PDN vs. 3D PDN 241.73MHz 243.59MHz Estimated package-die resonant frequency

8. Page  8 Current Source @ T1, Output Voltage @ T1  High-frequency resonance peak –Caused by the inductance of T2T connection and the local decoupling capacitance around it. –Highly-localized: beyond 40um the peak disappears (bypassed by other decaps around the current source) 23.62GHz Single TSV inductance: 34pH Local capacitance on M1: 1.159pF Estimated resonant frequency: 25.4GHz

9. Page  9 Current Source @ T1, Output Voltage @ T2  Small low-frequency impedance  Global mid-frequency resonance peak at package-T1 interface  Global high-frequency resonance peak at T1-T2 interface Effective TSV inductance: 2.83pH Total capacitance on T2: 25.96pF Estimated resonant frequency: 18.56GHz T1-T2: 20.26GHz pkg-T1: 245.5MHz

10. Page  10 Current Source @ T2, Output Voltage @ T2  Large impedance at current source location due to high-resistive M1  Global mid-frequency resonance peak at package-T1 interface –Caused by the anti-resonance between package inductance and total on-chip capacitance  Global high-frequency resonance peak at T1-T2 interface –Caused by the anti-resonance between T2T inductance and T2 total capacitance

11. Page  11 Current Source @ T2, Output Voltage @ T1  Large impedance at T2T locations –T2 current concentrates on the limited number of T2T locations  Local high-frequency resonance peak at T2T locations  Global mid-frequency resonance peak at package-T1 interface

12. Page  12 On-Chip Worst-Case PDN Noise Prediction Algorithm  Motivation –Local current on M1 is tiny  consider the distributed current effect –Obtain worst-case noise at multiple on-chip locations  Single-input worst-case PDN noise prediction algorithm [1] –Basic idea: dynamic programming  Multi-input worst-case PDN noise prediction algorithm –Extension of the single-input algorithm –Based on noise superimposition of the linear PDN model [1] P. Du, X. Hu, S. H. Weng, A. Shayan, X. Chen, A. E. Engin, and C.K Cheng. “Worst-Case Noise Prediction With Non-Zero Current Transition Times for Early Power Distribution System Verification,” In IEEE International Symposium on Quality Electronic Design, 2010

13. Page  13 On-Chip Worst-Case PDN Noise Flow Current source locations Simulate impulse responses All current sources traversed? Select an output node Calculate the worst-case noise More output nodes? Current constraints PDN netlist Pick one current source Worst-case noise map

14. Page  14 Worst-Case Noise Experiment Setting  Two-tier 3D PDN  9 uniformly distributed current sources on each tier  Same (x,y) current source locations on two tiers  First and last columns of the current sources locate at the same (x,y) coordinates as T2T connections  Current constraints –Maximum amplitude: 0.1mA –Minimum transition time: 10ps

15. Page  15 Worst-Case Noise Map on T1  Currents from T2 cause large noise around T2T interface.  Currents at T2T locations on T1 cause local high-frequency resonance peaks, making the noise worse. peak value

16. Page  16 Worst-Case Noise Map on T2  Uniform worst-case noise peak at nine current source locations  T2T distribution has no impact on the worst-case noise peak distributions on T2  Worst-case noise on T2 is 20 times of that on T1 peak value

17. Page  17 Rogue Waves: Time-Domain Worst-Case Noise Waveforms  Three output locations: –Blue: T2T location on T1 –Red: Away from T2T locations on T1 –Black: T2  Worst-case noise response: low-frequency oscillations followed by high-frequency oscillations  Rogue Wave  Worst-case noise response is dependent on the resonance behaviors of the output nodes and the spatial distribution of current sources –Output nodes on T2 (black): high-frequency oscillation followed by low-frequency oscillation due to global high-frequency resonance –Output nodes on T1 T2T location (blue): high-frequency oscillation followed by low-frequency oscillation due to local high-frequency resonance Away from T2T (red): no high-frequency oscillation

18. Page  18 Worst-Case Noise Flow Run Time Node #Impulse response simulation time Worst-case noise calculation time Total run time 758151.55 hr/current115 sec/node1.55 hr*N+115 sec*M N: number of current sources M: number of output nodes

19. Page  19 Conclusions  System-level analysis reveals the global resonance effects for 3D PDNs  Proposed on-chip 3D power grid model with detailed metal layer  Local resonance phenomenon due to T2T connection inductance and local capacitance is discovered with the detailed 3D power grid model  Worst-case noise calculation algorithm is extended to multiple input multiple output system  Worst-case noise map shows the spatial distribution of the worst-case noise in 3D PDNs  The “rogue wave” of worst-case noise response reflects the resonance behaviors at different locations of the 3D PDN

20. Page  20 Thank You! Q & A